Method for producing Group III nitride semiconductor, seed substrate and Group III nitride semiconductor crystal

US10693032B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10693032-B2
Application numberUS-201715713967-A
CountryUS
Kind codeB2
Filing dateSep 25, 2017
Priority dateSep 30, 2016
Publication dateJun 23, 2020
Grant dateJun 23, 2020

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Abstract

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The seed substrate comprises a base substrate and a base layer comprising a Group III nitride semiconductor formed on the base substrate, which has a high dislocation density region and a low dislocation density region. The planar pattern of the high dislocation density region is a honeycomb pattern. A hollow exists between the base substrate and the low dislocation density region. The object layer is grown through a flux method using the seed substrate. The high dislocation density region is melted back at an initial stage of crystal growth, and thereafter, the object layer is grown on the top surface of the low dislocation density region. A cavity remains between the high dislocation density region and the object layer. The presence of the cavity and the hollow makes easy to peel the object layer from the seed substrate.

First claim

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What is claimed is: 1. A method for producing a Group III nitride semiconductor by growing a Group III nitride semiconductor, through a flux method using a molten mixture of alkali metal and a Group III metal, on a seed substrate, wherein the seed substrate includes a base substrate and a base layer comprising a Group III nitride semiconductor grown on the base substrate, wherein a distribution of a dislocation density in the base layer has a two-dimensional periodic distribution in a direction parallel to a main surface thereof, wherein the base layer has a high dislocation density region and a low dislocation density region having a dislocation density lower than that of the high dislocation density region, and the distribution of the dislocation density has a two-dimensional periodic pattern comprising the high dislocation density region and the low dislocation density region, and wherein a method for producing the seed substrate comprises: forming a precursor layer of the base layer on the base substrate; forming a trench so as to reach the base substrate in the precursor layer by etching and making the remaining portion except the trench of the precursor layer the high dislocation density region; and forming the low dislocation density region by laterally regrowing a Group III nitride semiconductor from a side surface of the trench through metalorganic chemical vapor deposition (MOCVD) and covering the trench to make the base layer. 2. The method for producing a Group III nitride semiconductor according to claim 1 , wherein the high dislocation density region has a planar honeycomb pattern in which regular hexagons are arranged in an equilateral triangular lattice, and the low dislocation density region has a planar pattern which fills spaces among the regular hexagons of the high dislocation density region. 3. A method for producing a Group III nitride semiconductor by growing a Group III nitride semiconductor, through a flux method using a molten mixture of alkali metal and Group III metal, on a seed substrate, wherein the seed substrate includes a base substrate and a base layer comprising a Group III nitride semiconductor grown on the base substrate, and wherein a distribution of a dislocation density in the base layer has a two-dimensional periodic distribution in a direction parallel to the main surface thereof, wherein the base layer has a high dislocation density region and a low dislocation density region having a dislocation density lower than that of the high dislocation density region, and the distribution of the dislocation density has a two-dimensional periodic pattern comprising the high dislocation density region and the low dislocation density region, wherein a method for producing the seed substrate comprise: forming a precursor layer of the base layer on the base substrate; forming a trench so as to reach the base substrate in the precursor layer and making the remaining portion except the trench of the precursor layer the high dislocation density region; and forming the low dislocation density region b y laterally re win a Group III nitride semiconductor from a side surface of the trench and covering the trench to make the base layer, and wherein, in the forming the trench, the trench is formed so as to etch the base substrate, and, in the forming the low dislocation density region, a hollow remains between the base substrate and the low dislocation density region by preventing the trench formed on the base substrate from being filled with the low dislocation density region. 4. The method for producing a Group III nitride semiconductor according to claim 3 , wherein the high dislocation density region has a planar honeycomb pattern in which regular hexagons arranged in an equilateral triangular lattice, and the low dislocation density region has a planar pattern which fills spaces among the regular hexagons of the high dislocation density region. 5. The method for producing a Group III nitride semiconductor according to claim 3 , wherein the high dislocation density region is melted back at an initial stage of crystal growth of an object layer comprising a Group III nitride semiconductor through a flux method, and thereafter, the object layer is formed so as to cover holes formed due to melting back on a top surface of the low dislocation density region, and to remain cavities between the object layer and the high dislocation density region. 6. The method for producing a Group III nitride semiconductor according to claim 4 , wherein the high dislocation density region is melted back at an initial stage of crystal growth of an object layer comprising a Group III nitride semiconductor through a flux method, and thereafter, the object layer is formed so as to cover holes formed due to melting back on a top surface of the low dislocation density region, and to remain cavities between the object layer and the high dislocation density region. 7. The method for producing a Group III nitride semiconductor according to claim 1 , wherein the high dislocation density region is melted back at an initial stage of crystal growth of an object layer comprising a Group III nitride semiconductor through a flux method, and thereafter, the object layer is formed so as to cover holes formed due to melting back on a top surface of the low dislocation density region, and to remain cavities between the object layer and the high dislocation density region. 8. The method for producing a Group III nitride semiconductor according to claim 2 , wherein the high dislocation density region is melted back at an initial stage of crystal growth of an object layer comprising a Group III nitride semiconductor through a flux method, and thereafter, the object layer is formed so as to cover holes formed due to melting back on a top surface of the low dislocation density region, and to remain cavities between the object layer and the high dislocation density region. 9. The method for producing a Group III nitride semiconductor according to claim 3 , wherein the average dislocation density of the base layer is 5×10 8 /cm 2 or less. 10. The method for producing a Group III nitride semiconductor according to claim 3 , wherein the seed substrate has a diameter of two inches or more.

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Classifications

  • comprising nitrides, e.g. GaN · CPC title

  • using as solvent a component of the crystal composition · CPC title

  • Solar cells from Group III-V materials · CPC title

  • Metal solvents · CPC title

  • characterised by the substrate · CPC title

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What does patent US10693032B2 cover?
The seed substrate comprises a base substrate and a base layer comprising a Group III nitride semiconductor formed on the base substrate, which has a high dislocation density region and a low dislocation density region. The planar pattern of the high dislocation density region is a honeycomb pattern. A hollow exists between the base substrate and the low dislocation density region. The object l…
Who is the assignee on this patent?
Toyoda Gosei Kk
What technology area does this patent fall under?
Primary CPC classification H10F71/1278. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 23 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).