Trench formation for dielectric filled cut region

Patent metadata

Field	Value
Publication number	US-9601335-B2
Application number	US-201615282836-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Jul 27, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

First claim

The invention claimed is:

1. A method for forming a gate cut region, comprising:
forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate;
forming a dummy gate dielectric and a dummy gate conductor in the trench;
planarizing a top surface to reach the hard mask;
patterning the dummy gate conductor to form a cut trench in a cut region;
recessing the dummy gate conductor to expose a shallow trench isolation region in the substrate;
filling the cut trench with a first dielectric material;
removing the dummy layer;
forming spacers about a gate line;
filling gaps using an interlevel dielectric (ILD) deposition;
opening up the gate line to expose and remove the dummy gate conductor from the tapered profile gate line trench;
depositing a gate dielectric and gate conductor in the tapered profile gate line trench; and
forming a gate cap layer to cap a gate structure and provide a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

2. The method as recited in claim 1 , wherein the forming a tapered profile gate line trench includes etching the tapered profile gate line trench using a lithography, etch, lithography, etch (LELE) process.

3. The method as recited in claim 1 , wherein the first dielectric and the second dielectric include silicon nitride.

4. The method as recited in claim 1 , further comprising epitaxially growing source and drain regions adjacent to the spacers.

5. The method as recited in claim 1 , wherein the dummy gate dielectric provides an etch stop layer for removing the dummy layer.

6. The method as recited in claim 1 , wherein recessing the dummy gate conductor includes forming a deeper recess at a central portion of the cut region than side regions and recessing the central portion to first expose the shallow trench isolation region.

7. The method as recited in claim 1 , further comprising forming an interlevel dielectric layer over the gate line and etching contact holes in the ILD stopping on the second dielectric material in the cut region.

8. A method for forming a gate cut region, comprising:
forming shallow trench isolation (STI) regions in a substrate wherein one STI region corresponds to a central portion of a cut region;
forming a hard mask, a dummy layer and a dummy dielectric on the substrate;
etching a tapered profile gate line trench through the hard mask, the dummy layer and the dummy dielectric;
forming a dummy gate dielectric and a dummy gate conductor in the trench;
planarizing a top surface to reach the hard mask;
patterning the dummy gate conductor to form a cut trench in the cut region;
recessing the dummy gate conductor to expose the one STI region in the substrate;
filling the cut trench with a first dielectric material;
removing the dummy layer;
forming spacers about a gate line exposed by removing the dummy layer;
epitaxially growing source and drain regions adjacent to the spacers;
filling gaps using an interlevel dielectric (ILD) deposition;
planarizing the ILD to open up the gate line to expose and remove the dummy gate conductor from the tapered profile gate line trench;
depositing a gate dielectric and gate conductor in the tapered profile gate line trench; and
forming a gate cap layer to cap a gate structure and provide a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

9. The method as recited in claim 8 , wherein the etching a tapered profile gate line trench includes etching the tapered profile gate line trench using a lithography, etch, lithography, etch (LELE) process.

10. The method as recited in claim 8 , wherein the first dielectric and the second dielectric include silicon nitride.

11. The method as recited in claim 8 , wherein the dummy gate dielectric provides an etch stop layer for removing the dummy layer.

12. The method as recited in claim 8 , wherein recessing the dummy gate conductor includes forming a deeper recess at a central portion of the cut region than side regions and recessing the central portion to first expose the one STI region.

13. The method as recited in claim 8 , further comprising forming an interlevel dielectric layer over the gate line and etching contact holes in the ILD stopping on the second dielectric material in the cut region.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Greene Andrew M
• Jung Ryan O
• Xie Ruilong
• Xu Peng

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title