Memory structure

Patent metadata

Field	Value
Publication number	US-10692875-B2
Application number	US-201816177812-A
Country	US
Kind code	B2
Filing date	Nov 1, 2018
Priority date	Oct 15, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.

First claim

What is claimed is:

1. A memory structure, comprising:
a substrate;
at least one stacked gate structure located on the substrate and comprising a control gate, wherein the control gate extends in a first direction;
a first spacer conductive layer located on one sidewall of the control gate and electrically insulated from the control gate, wherein the first spacer conductive layer comprises a first merged spacer portion and a first non-merged spacer portion, and a line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion; and
a first contact connected to the first merged spacer portion.

2. The memory structure according to claim 1 , wherein the line width of the first merged spacer portion is 1.2 to 2 times the line width of the first non-merged spacer portion.

3. The memory structure according to claim 1 , wherein the substrate comprises a contact landing region.

4. The memory structure according to claim 3 , wherein the control gate located in the contact landing region has a notch, and the first merged spacer portion is located in the notch.

5. The memory structure according to claim 3 , wherein a line width of the control gate in the contact landing region is greater than a line width of the control gate outside the contact landing region.

6. The memory structure according to claim 3 , further comprising:
active regions extending in a second direction, wherein the first direction intersects the second direction, and the contact landing region is located between two adjacent active regions.

7. The memory structure according to claim 1 , wherein when the number of the at least one stacked gate structure is multiple, each of the stacked gate structures comprises the control gate, two adjacent first spacer conductive layers are disposed between two adjacent control gates, and the two adjacent first spacer conductive layers share the first merged spacer portion.

8. The memory structure according to claim 7 , wherein a first spacing between the two adjacent control gates is less than a second spacing between the two adjacent control gates, and the first merged spacer portion is located in a trench having the first spacing between the two adjacent control gates.

9. The memory structure according to claim 1 , further comprising:
an isolation structure located in the substrate.

10. The memory structure according to claim 9 , wherein the first merged spacer portion is located above the isolation structure.

11. The memory structure according to claim 1 , further comprising:
a second spacer conductive layer located on the other sidewall of the control gate and electrically insulated from the control gate.

12. The memory structure according to claim 11 , wherein the second spacer conductive layer comprises a second merged spacer portion and a second non-merged spacer portion, and a line width of the second merged spacer portion is greater than a line width of the second non-merged spacer portion.

13. The memory structure according to claim 12 , wherein the line width of the second merged spacer portion is 1.2 to 2 times the line width of the second non-merged spacer portion.

14. The memory structure according to claim 12 , wherein when the number of the at least one stacked gate structure is multiple, each of the stacked gate structures comprises the control gate.

15. The memory structure according to claim 14 , wherein two adjacent second spacer conductive layers are disposed between two adjacent control gates.

16. The memory structure according to claim 15 , wherein the two adjacent second spacer conductive layers share the second merged spacer portion.

17. The memory structure according to claim 14 , a first spacing between two adjacent control gates is less than a second spacing between the two adjacent control gates, and the second merged spacer portion is located in a trench having the first spacing between the two adjacent control gates.

18. The memory structure according to claim 12 , further comprising:
a second contact connected to the second merged spacer portion.

19. The memory structure according to claim 1 , wherein the at least one stacked gate structure further comprises:
a charge storage layer located between the substrate and the control gate and electrically insulated from the substrate and the control gate.

20. The memory structure according to claim 19 , wherein the charge storage layer comprises a charge trapping layer or a floating gate.

Assignees

• United Microelectronics Corp

Inventors

• Xiang Wang
• Hsu Chia-Ching
• Huang Chun-Sung
• Tseng Yung-Lin
• Liu wei-chang
• Wang Shen-De

Classifications

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/30 Primary

  characterised by the memory core region · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/30

  characterised by the memory core region · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title