Self-aligned flash memory device

Patent metadata

Field	Value
Publication number	US-9978761-B2
Application number	US-201615216872-A
Country	US
Kind code	B2
Filing date	Jul 22, 2016
Priority date	May 27, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.

First claim

What is claimed is:

1. A method of forming a flash memory device, comprising:
providing a substrate including a pair of gate stacks disposed thereover, wherein the gate stacks include floating gates and control gates arranged over the floating gates and separated from the floating gates by a control dielectric;
forming a conductive material over the substrate and along a topology of the gate stacks;
forming a masking layer to cover a first portion of the conductive material between the gate stacks and to expose a second portion of the conductive material on opposite sides of the gate stacks;
performing a first etching process to lower the second portion of the conductive material;
removing the masking layer; and
performing a series of etching processes to form word lines on opposite sides of the gate stacks and an erase gate between the gate stacks;
wherein a first height of the word lines is smaller than a second height of the erase gate.

2. The method of claim 1 , wherein the series of etching processes comprises an argon ion treatment process that reduces an upper corner of the conductive material locating at opposite sides of the pair of gate stacks while raises a middle region of the conductive material between the pair of gate stacks by a byproduct of the argon ion treatment process.

3. The method of claim 1 , wherein the series of etching processes comprises an anisotropic etch back process that removes excessive lateral portions of the conductive material and forms a sidewall spacer along the word lines.

4. The method of claim 1 , wherein the word lines are formed to have an upper surface that monotonically trends upwardly from an outer side opposite to the gate stack to an inner side closer to the gate stack.

5. The method of claim 1 , wherein the erase gate is formed to have a concave top surface.

6. The method of claim 1 , further comprising:
performing a second etching process to uniformly lower the first and second portions of the conductive material after removing the masking layer.

7. The method of claim 6 , wherein the second etching process comprises a dry etch including halogen, oxygen, and fluoride gases.

8. The method of claim 1 , wherein the masking layer is a photoresist material and is removed in-situ with the first etching process.

9. A method of forming a flash memory device, comprising:
providing a substrate including a pair of gate stacks disposed thereover, wherein the gate stacks include floating gates and control gates arranged over the floating gates;
forming a conductive material over the substrate and along a topology of the gate stacks;
performing an ion treatment process to the conductive material such that an upper corner of the conductive material locating at opposite sides of the pair of gate stacks is lowered while a middle region of the conductive material between the pair of gate stacks is raised by a byproduct of the ion treatment process; and
performing an etch back process to the conductive material vertically to form word lines on opposite sides of the gate stacks and an erase gate between the gate stacks.

10. The method of claim 9 , wherein the ion treatment process and the etch back process are performed in-situ in one dry etching chamber.

11. The method of claim 9 , wherein the ion treatment process comprises an argon (Ar) ion bombardment process.

12. The method of claim 9 , wherein an oxidation process is involved in the etch back process to form a sidewall spacer along an upper sidewall of the conductive material and have the word lines self-aligned.

13. The method of claim 9 , further comprising:
forming a dielectric liner over the conductive material; and
performing an etch through the dielectric liner to remove lateral portions and to leave a sidewall portion of the dielectric liner to form a sidewall spacer along sidewalls of the word lines to be formed.

14. The method of claim 9 , further comprising:
forming source/drain regions in the substrate, wherein the source/drain regions are arranged between the pair of gate stacks and about outer sidewalls of the word lines;
forming an interlayer dielectric (ILD) layer over the pair of gate stacks and the word lines; and
forming contacts extending through the ILD layer to the source/drain regions.

15. A method of forming a flash memory device, comprising:
forming a gate stack separated from a substrate by a gate dielectric, the gate stack being formed by forming a control gate separated from a floating gate by a control gate dielectric;
forming a conductive material over the substrate and along a topology of the gate stacks;
forming a masking layer to cover a first portion of the conductive material on a first side of the gate stacks and to expose a second portion of the conductive material on a second side of the gate stacks opposite to the first side;
performing a first etching process to lower the second portion of the conductive material; and
performing a second etching process to form an erase gate on the first side and a word line on the second side of the gate stack.

16. The method of claim 15 , further comprising performing an ion treatment process to the conductive material prior to performing the second etching process such that an upper corner of the conductive material locating at one of the gate stack is lowered while the conductive material at the other side of the gate stack is raised by a byproduct of the ion treatment process.

17. The method of claim 15 , wherein the erase gate is formed having a concave top surface.

18. The method of claim 15 , wherein a word line height is about 70% to about 80% of an erase gate height.

19. The method of claim 9 , prior to performing the ion treatment process, further comprising:
forming a masking layer to cover a first portion of the conductive material between the gate stacks and to expose a second portion of the conductive material on opposite sides of the gate stacks;
performing a first etching process to lower the second portion of the conductive material; and
removing the masking layer.

20. The method of claim 19 , further comprising:
performing a second etching process to uniformly lower the first and second portions of the conductive material after removing the masking layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Ming-Chyi
• Liu Shih-Chang
• Chen Sheng-Chieh

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H01L27/1052

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic

• H01L27/11526 Primary

  Electricity · mapped topic