Semiconductor device with nanowires in different regions at different heights

Patent metadata

Field	Value
Publication number	US-9583583-B2
Application number	US-201514969025-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Oct 10, 2012
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a structure having a first sacrificial layer, a first active layer, a second sacrificial layer and a second active layer sequentially formed on a substrate, wherein a first width of the first active layer is greater than a second width of the second active layer so that the first active layer includes an extending part that extends from one side relative to the second active layer; and
a first gate-all-around device on the extending part of the first active layer and including a first nanowire, wherein a thickness of the first nanowire is substantially equal to a thickness of the second active layer.

2. The semiconductor device of claim 1 , further comprising: a second gate-all-around device on the second active layer and including a second nanowire.

3. The semiconductor device of claim 2 , wherein a first threshold voltage of the first gate-all-around device is different from a second threshold voltage of the second gate-all-around device.

4. The semiconductor device of claim 2 , wherein a first thickness of the first nanowire is different from a second thickness of the second nanowire.

5. The semiconductor device of claim 2 , wherein a first gate of the first gate-all-around device is separated from a second gate of the second gate-all-around device.

6. The semiconductor device of claim 2 , wherein the second gate all around device has another nanowire adjacent the second nanowire, and a gate of the second gate-all-around device applies a same signal to the second nanowire and the another nanowire.

7. The semiconductor device of claim 1 , wherein at least one of the first active layer or the second active layer includes Si and wherein at least one of the first sacrificial layer or the second sacrificial layer includes SiGe.

8. The semiconductor device of claim 1 , wherein source/drain areas of the first gate-all-around device are raised source/drain areas.

9. The semiconductor device of claim 1 , further comprising a stress layer on the first gate-all-around device.

Assignees

• Samsung Electronics Co Ltd
• Univ Seoul Nat R & Db Found
• Seoul Nat Univ R & Db Found

Inventors

• Sun Min-Chul
• Park Byung-Gook

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/276

  Lateral overgrowth · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/00

  Field-effect transistors [FET] (insulated-gate bipolar transistors H10D12/00) · CPC title