Forming uniform WF metal layers in gate areas of nano-sheet structures

Patent metadata

Field	Value
Publication number	US-9685522-B1
Application number	US-201615093952-A
Country	US
Kind code	B1
Filing date	Apr 8, 2016
Priority date	Apr 8, 2016
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Methods for forming uniform WF metal layers in gate areas of NS structures in a NS FET and the resulting devices are disclosed. Embodiments include providing NS structures, parallel to and spaced from each other, in a substrate; conformally forming gate dielectric and metal layers, respectively, on all surfaces in a gate area of each NS structure; forming a barrier layer on surfaces in the gate area of each NS structure except on surfaces in between the NS structures by PVD or PECVD; annealing the NS structures including the gate dielectric and metal layers; removing the barrier and metal layers from all surfaces; and forming a WF metal layer on all surfaces in the gate area of each NS structure.

First claim

What is claimed is:

1. A method comprising:
providing nano-sheet (NS) structures, parallel to and spaced from each other, in a substrate;
conformally forming gate dielectric and metal layers, respectively, on all surfaces in a gate area of each NS structure;
forming a barrier layer on surfaces in the gate area of each NS structure except on surfaces in between the NS structures by physical vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD);
annealing the NS structures including the gate dielectric and metal layers;
removing the barrier and metal layers from all surfaces; and
forming a work-function (WF) metal layer on all surfaces in the gate area of each NS structure.

2. The method according to claim 1 , comprising forming the barrier layer by PVD of a silicon layer.

3. The method according to claim 1 , comprising forming the barrier layer by PECVD of silicon nitride (SiN).

4. The method according to claim 1 , wherein the barrier layer is an oxygen barrier layer.

5. The method according to claim 1 , comprising forming the gate dielectric layer by atomic layer deposition (ALD) of a high-k dielectric layer.

6. The method according to claim 5 , comprising forming the gate dielectric layer of hafnium oxide.

7. The method according to claim 1 , further comprising forming source/drain regions adjacent to the gate area on each NS structure.

8. The method according to claim 1 , comprising forming the gate metal layer by ALD.

9. The method according to claim 8 , comprising forming the gate metal layer of titanium nitride (TiN) to a thickness of 10 to 20 angstroms (Å).

10. The method according to claim 1 , wherein spaces between NS structures are less than 5 nanometers (nm).

11. A device comprising:
nano-sheet (NS) structures, parallel to and spaced from each other, in a substrate;
a gate dielectric layer annealed on all surfaces in a gate area of each NS structure; and
a work-function (WF) metal layer formed on all surfaces in the gate area of each NS structure.

12. The device according to claim 11 , comprising source/drain regions adjacent to the gate area on each NS structure.

13. The device according to claim 11 , wherein the gate dielectric layer is hafnium oxide.

14. A method comprising:
providing nano-sheet (NS) structures, parallel to and spaced from each other, in a substrate;
conformally forming high-k gate dielectric and metal layers, respectively, on all surfaces in a gate area of each NS structure;
forming an oxygen barrier layer on surfaces in the gate area of each NS structure except on surfaces in between the NS structures by physical vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD);
annealing the NS structures including the gate dielectric and metal layers;
removing the oxygen barrier and metal layers from all surfaces; and
forming a work-function (WF) metal layer on all surfaces in the gate area of each NS structure.

15. The method according to claim 14 , comprising forming the oxygen barrier layer by PVD of a silicon layer.

16. The method according to claim 14 , comprising forming the oxygen barrier layer by PECVD of silicon nitride (SiN).

17. The method according to claim 14 , comprising forming the gate dielectric layer by atomic layer deposition (ALD) of hafnium oxide.

18. The method according to claim 14 , comprising forming source/drain regions adjacent to the gate area on each NS structure.

19. The method according to claim 14 , comprising forming the gate metal layer of titanium nitride (TiN).

20. The method according to claim 19 , comprising forming the gate metal layer to a thickness of 10 to 20 angstroms (Å).

Assignees

• Globalfoundries Inc

Inventors

• Kim Hoon
• Sung Min Gyu
• Xie Ruilong
• Park Chanro

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L29/42392 Primary

  Electricity · mapped topic

• H01L21/28088

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/517

  Electricity · mapped topic