Formation of VTFET fin and vertical fin profile

Patent metadata

Field	Value
Publication number	US-10692776-B2
Application number	US-201816181977-A
Country	US
Kind code	B2
Filing date	Nov 6, 2018
Priority date	Nov 6, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.

First claim

The invention claimed is:

1. A method for forming a semiconductor device, comprising:
etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer; and
forming a second semiconductor layer around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer; and
forming a gate structure over the fins.

2. The method as recited in claim 1 , wherein growing the second semiconductor layer includes:
growing a first semiconductor material below the semiconductor portions of the fins in a first region to form a p-type semiconductor layer beneath the fins in the first region; and
growing a second semiconductor material below the semiconductor portions of the fins in a second region to form a n-type semiconductor layer beneath the fins in the second region such that the p-type semiconductor layer and the n-type semiconductor layer have respective top surfaces that are coplanar and form a square profile relative to each of the vertical fin sidewalls.

3. The method as recited in claim 1 , wherein forming the gate structure includes:
forming a first gate structure over fins in a first region to form first field effect transistors (FET); and
forming a second gate structure over fins in a second region to form second FETs.

4. The method as recited in claim 3 , wherein the first FETs are p-type FETs (pFETs) and the second FETs are n-type FETs (nFETs).

5. The method as recited in claim 1 , wherein the intermediate layer includes silicon germanium (SiGe).

6. The method as recited in claim 1 , further including recessing the tapered bottom portions of the fins to be narrower than the semiconductor portions of the fins.

7. The method as recited in claim 1 , further including doping the semiconductor material.

8. The method as recited in claim 1 , further including:
masking a first region of the active region with a mask;
epitaxially growing a first semiconductor material from the tapered bottom portions in the first region;
removing the mask from the first region;
masking a second region of the active region with a second mask; and
epitaxially growing a second semiconductor material from the tapered bottom portions in the second region.

9. The method as recited in claim 8 , wherein the first region and the second region are adjacent.

10. A method for forming a semiconductor device, comprising:
etching fins into a bulk substrate in an active region, the active region including a first region and a second region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer;
growing a second semiconductor layer from the tapered bottom portions below the semiconductor portions of the fins in the first region;
growing a third semiconductor layer from the tapered bottom portions below the semiconductor portions of the fins in the second region such that the first semiconductor layer and the second semiconductor layer have respective top surfaces proximal to the semiconductor portions of the fins that is substantially parallel to a top surface of the base layer;
forming a first gate structure over the fins in the first region to form first field effect transistors (FET); and
forming a second gate structure over the fins in the second region to form second FETs.

11. The method as recited in claim 10 , wherein the first FETs are p-type FETs (pFETs) and the second FETs are n-type FETs (nFETs).

12. The method as recited in claim 10 , wherein the intermediate layer includes silicon germanium (SiGe).

13. The method as recited in claim 10 , further including recessing the tapered bottom portions of the fins to be narrower than the semiconductor portions of the fins.

14. The method as recited in claim 10 , further including doping the second semiconductor layer with n-type dopants.

15. The method as recited in claim 10 , further including:
masking the first region of the active region with a mask;
epitaxially growing the first semiconductor layer from the tapered bottom portions in the first region;
removing the mask from the first region;
masking the second region of the active region with a second mask; and
epitaxially growing the third semiconductor layer from the tapered bottom portions in the second region.

16. The method as recited in claim 15 , wherein the first region and the second region are adjacent.

Assignees

• IBM

Inventors

• Miller Eric R
• Bergendahl Marc
• Cheng Kangguo
• Mignot Yann

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D84/0195

  the components including vertical IGFETs · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title