Differential Phase and amplitude detector

Patent metadata

Field	Value
Publication number	US-10690708-B2
Application number	US-201816115435-A
Country	US
Kind code	B2
Filing date	Aug 28, 2018
Priority date	Aug 28, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A differential phase and amplitude detector circuit is presented. Two source follower circuits respectively based on NMOS and PMOS transistors are used to charge and discharge a sampling capacitor asymmetrically to provide a measurement of phase and/or amplitude difference between two signals of a substantially same frequency. The measurement can be made in one cycle, with the charging of the sampling capacitor performed during a first half cycle where a voltage difference between the two signals is positive, and the discharging during a second half cycle where a voltage difference between the two signals is negative. Biasing of the two source follower circuits enable an excess current flow between the two transistors of the two source follower circuits beyond a biasing current of the transistors to charge the sampling capacitor during the first half cycle, and disable the excess current flow between the two transistors during the second half cycle.

First claim

The invention claimed is:

1. A circuit arrangement comprising:
a first differential phase and amplitude detector, comprising:
an NMOS transistor;
a PMOS transistor;
a first input coupled to a gate node of the NMOS transistor, the first input configured for receiving a first radio frequency (RF) signal having a first voltage;
a second input coupled to a gate node of the PMOS transistor, the second input configured for receiving a second RF signal having a second voltage;
a differential output comprising a first node coupled to a source node of the NMOS transistor and a second node coupled to a source node of the PMOS transistor, and
a sampling capacitor coupled between the first node and the second node;

wherein:
when the first voltage and the second voltage are equal, a first DC biasing current flows through the NMOS transistor, a second DC biasing current flows through the PMOS transistor, and no current flows between the first node and the second node,
when the first voltage is larger than the second voltage, an excess current sourced by the NMOS transistor and sinked by the PMOS transistor flows from the first node to the second node to charge the sampling capacitor, the excess current having a magnitude that is substantially larger than the first DC biasing current, and
when the first voltage is smaller than the second voltage, no current flows between the NMOS transistor and the PMOS transistor, and the sampling capacitor is discharged by a portion of the first and the second DC biasing currents that flow from the second node to the first node.

2. The circuit arrangement according to claim 1 , wherein:
the first RF signal and the second RF signal have a substantially same frequency, and
during a first half cycle of the frequency, the excess current charges the sampling capacitor by a charging voltage that represents a positive voltage difference between the first voltage and the second voltage.

3. The circuit arrangement according to claim 1 , wherein:
during a second half cycle of the frequency, the portion of the first and the second DC biasing currents discharge the sampling capacitor by a discharging voltage that is substantially smaller than the charging voltage.

4. The circuit arrangement according to claim 3 , wherein a ratio of the portion of the first and the second DC biasing currents to the excess current is about ⅕ or smaller.

5. The circuit arrangement according to claim 2 , wherein:
during the first half cycle of the frequency, the excess current charges the sampling capacitor by a voltage that is equal to the positive voltage difference between the first voltage and the second voltage.

6. The circuit arrangement according to claim 2 , wherein:
the positive voltage difference represents an amplitude difference between the first RF signal and the second RF signal.

7. The circuit arrangement according to claim 2 , wherein:
the positive voltage difference represents a phase difference between the first RF signal and the second RF signal.

8. The circuit arrangement according to claim 2 , wherein:
the NMOS transistor is configured as a first source follower circuit for controlling a voltage at the first node based on the first voltage, the first node coupled to a source node of the NMOS transistor and the first voltage provided to a gate of the NMOS transistor, and
the PMOS transistor is configured as a second source follower circuit for controlling a voltage at the second node based on the second voltage, the second node coupled to a source node of the PMOS transistor and the second voltage provided to a gate of the PMOS transistor.

9. The circuit arrangement according to claim 1 , wherein the first differential phase and amplitude detector further comprises:
a first current source coupled between the first node and a reference ground, the first current source providing the first DC biasing current; and
a second current source coupled between a supply voltage and the second node, the second current source providing the second DC biasing current.

10. The circuit arrangement according to claim 1 , wherein a ratio of the first DC biasing current to the second DC biasing current is based on a ratio of a size of the NMOS transistor to a size of the PMOS transistor.

11. The circuit arrangement according to claim 1 , wherein the first differential phase and amplitude detector further comprises a biasing voltage control circuit configured to control a biasing voltage to the NMOS transistor to maintain a constant offset between voltages at the first and second nodes when the first voltage and the second voltage are zero.

12. The circuit arrangement according to claim 11 , wherein the biasing voltage control circuit comprises:
a second differential phase and amplitude detector that is a duplicate of the first differential phase and amplitude detector except configured to respectively receive a zero volts signal at the first input and the second input; and
a voltage difference detector circuit coupled to the first and second nodes of the second differential phase and detector circuit, the voltage difference detector circuit configured to generate, at an output of the voltage difference detector circuit, a voltage that is proportional to a difference between voltages at the first and the second nodes,
wherein the biasing voltage to the NMOS transistor of the first and the second differential phase and amplitude detector is based on the voltage at the output of the voltage difference detector circuit.

13. The circuit arrangement according to claim 1 , further comprising:
a second differential phase and amplitude detector that is a duplicate of the first differential phase and amplitude detector except configured to respectively receive the second radio frequency signal and the first radio frequency signal at the first input and the second input; and
a differential combiner circuit coupled to respective differential outputs of the first and second differential phase and amplitude detectors and generate therefrom a combined differential voltage at a combined differential output.

14. The circuit arrangement according to claim 13 , wherein the differential combiner circuit comprises:
a first pair of series connected resistors coupled to one another via respective first terminals at a first common node, and coupled via respective second terminals to respective first nodes of the first and second differential phase and amplitude detectors;
a second pair of series connected resistors coupled to one another via respective first terminals at a second common node, and coupled via respective second terminals to respective second nodes of the first and second differential phase and amplitude detectors; and
an output capacitor coupled between the first and the second common nodes, a voltage across the output capacitor being the combined differential voltage.

15. The circuit arrangement according to claim 13 , wherein the differential combiner circuit provides a low pass filtering function or an integrating function to generate an indication of an average of phase and/or amplitude difference between the first RF signal and the second RF signal.

16. A method for detecting a phase and amplitude difference between two RF signals, the method comprising:
providing an NMOS transistor configured as a first source follower circuit for controlling a voltage at a first node based on a first voltage of a first input RF signal;
providing a PMOS transistor configured as a second source follower circuit for controlling a voltage at a second node based on a second voltage of a sec

Assignees

• Psemi Corp

Inventors

• Adamski Jaroslaw

Classifications

• G01R25/02 Primary

  in circuits having distributed constants · CPC title

• G01R23/005

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing phase or frequency of 2 mutually independent oscillations in demodulators) · CPC title

• G01R25/005 Primary

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal · CPC title