Switching power source, method and control chip for controlling the same
US-2015381058-A1 · Dec 31, 2015 · US
Area efficient single capacitor CMOS relaxation oscillator
US8970313B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8970313-B2 |
| Application number | US-201213644490-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 4, 2012 |
| Priority date | Oct 2, 2012 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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Methods and circuits for CMOS relaxation oscillators are disclosed. A single capacitive element, a single current source and a switching network are utilized. A switching network of the oscillator allows both nodes of the capacitive element to rise and fall between a positive and a negative voltage with respect to ground supply, without causing leakage to substrate or risk of latch-up, i.e. the inadvertent creation of a low-impedance path. The oscillator requires minimum silicon area, has an improved duty cycle, is particular useful for implementing lower frequency clocks and is enabled for smaller technology nodes, lower than 250 nm, due to lower supply voltage.
First claim
Opening claim text (preview).
What is claimed is: 1. A method to achieve CMOS oscillators enabled for small technology nodes below 250 nm comprising the steps of (1) providing a relaxation oscillator comprising only one capacitive element, a current source configured to providing current for charging the capacitive element, a comparator, a logic circuitry, and a CMOS switching network, configured to alternatingly charging one terminal of the capacitive element up to a level of a reference level and connecting…
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- H03K3/0231Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8970313B2 cover?
- Methods and circuits for CMOS relaxation oscillators are disclosed. A single capacitive element, a single current source and a switching network are utilized. A switching network of the oscillator allows both nodes of the capacitive element to rise and fall between a positive and a negative voltage with respect to ground supply, without causing leakage to substrate or risk of latch-up, i.e. the…
- Who is the assignee on this patent?
- Dialog Semiconductor Gmbh
- What technology area does this patent fall under?
- Primary CPC classification H03K3/0231. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).