Mismatch detection using replica circuit

Patent metadata

Field	Value
Publication number	US-9864000-B2
Application number	US-201615341955-A
Country	US
Kind code	B2
Filing date	Nov 2, 2016
Priority date	Sep 30, 2013
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.

First claim

What is claimed is:

1. A circuital arrangement, comprising:
a sensing circuit;
a first radio frequency (RF) path coupled, through one or more sensing points of the first RF path, to the sensing circuit, the first RF path comprising a first amplifying circuit; and
at least one second RF path coupled, through one or more sensing points of the second RF path in correspondence of the one or more sensing points of the first RF path, to the sensing circuit, the second RF path comprising a second amplifying circuit, the second amplifying circuit being a reduced size replica of the first amplifying circuit,
wherein the sensing circuit is adapted to sense a difference between one or more operating characteristics of the first RF path, sensed at the one or more sensing points of the first RF path, and one or more reference operating characteristics of the second RF path, sensed at the corresponding one or more sensing points of the second RF path.

2. The circuital arrangement according to claim 1 , wherein:
the one or more operating characteristics of the first RF path are affected by a set of operating variables, and
the second RF path is configured so that one or more reference operating characteristics of the second RF path are affected by a subset of the operating variables.

3. The circuital arrangement according to claim 2 , wherein the set of operating variables comprises one or more of: a) a load to the first/second RF paths, b) a local temperature at the first/second amplifying circuits, c) hot carrier injection (HCI) effect on devices of the first/second amplifying circuits, d) transient effects on the first/second amplifying circuits, e) floating body effects on devices of the first/second amplifying circuits, f) different operating modes of the first/second RF paths, and g) different frequencies of operation of the first/second RF paths.

4. The circuital arrangement according to claim 2 , wherein the operating characteristics of the first amplifying circuit and the operating characteristics of the second amplifying circuit are related according to a known mapping function over the set of operating variables.

5. The circuital arrangement according to claim 2 , wherein the one or more operating characteristics comprise one or more of: a) a signal modulation characteristic, b) a signal linearity characteristic, c) a signal distortion characteristic, d) a signal magnitude characteristic, e) a signal phase characteristic, f) a transient response characteristic, g) a temperature characteristic, and e) bias conditions, including bias voltages and bias currents.

6. The circuital arrangement according to claim 2 , wherein:
the first RF path is configured to transmit an RF signal at an output node of the first RF path through a matching impedance coupled to the output node of the first RF path, and
the second RF path is configured to terminate an RF signal at an output node of the second RF path through a terminating impedance coupled to the output node of the second RF path.

7. The circuital arrangement according to claim 2 , wherein the sensing circuit senses signals at the one or more sensing points of the first RF path in correspondence of the one or more operating characteristics of the first RF path, and senses signals at the one or more sensing points of the second RF path in correspondence of the one or more reference operating characteristics of the second RF path.

8. The circuital arrangement according to claim 7 , wherein the sensed signals are one or more of: a) a voltage signal, b) a current signal, and c) a power signal.

9. The circuital arrangement according to claim 7 , wherein the first RF path and the second RF path further comprise control inputs configured to receive control signals to affect the one or more operating characteristics.

10. The circuital arrangement according to claim 9 , wherein the control signals are based on the sensed signals.

11. The circuital arrangement according to claim 10 , wherein the reduced size of the second amplifying circuit is about 1/100 th or less a size of the first amplifying circuit, such as a current flow and a power consumption of the second amplifying circuit is about 1/100 th or less of a current flow and a power consumption of the first amplifying circuit.

12. The circuital arrangement according to claim 11 , wherein the first and the second amplifying circuits respectively comprise a first cascode stack and a second cascode stack.

13. The circuital arrangement according to claim 12 , wherein transistors of first cascode stack and transistors of the second cascode stack differ in one or more of: a) a channel width, and b) a channel length.

14. The circuital arrangement according to claim 10 , wherein the first RF path and the second RF path each further comprise an output signal processing circuit coupled to a respective output node of the first amplifying circuit and the second amplifying circuit.

15. The circuital arrangement according to claim 14 , wherein the first RF path and the second RF path each further comprise an input signal processing circuit coupled to a respective input node of the first amplifying circuit and the second amplifying circuit.

16. The circuital arrangement according to claim 15 , wherein the input signal processing circuit and the output signal processing circuit are configured to affect one or more of: a) a signal amplitude, b) a signal phase, and c) an impedance presented to the respective input node and output node.

17. The circuital arrangement according to claim 16 , wherein one or both of the input signal processing circuit and the output signal processing circuit is adapted to be controlled by the control signals.

18. The circuital arrangement according to claim 16 , wherein the input signal processing circuit and the output signal processing circuit each comprise one or more of: a) a tunable match circuit, b) a fixed match, c) a variable attenuator, d) a fixed attenuator, e) a variable phase shifter circuit, and f) a filter.

19. The circuital arrangement according to claim 18 , wherein the one or more of the input signal processing circuit and the output signal processing circuit comprise one or more of a) a digital tunable capacitor (DTC), and b) a digital tunable inductor (DTL).

20. The circuital arrangement according to claim 10 , wherein the first RF path and the second RF path each comprises an amplifier biasing circuit configured to bias a respective one of the first amplifying circuit and the second amplifying circuit.

21. The circuital arrangement according to claim 20 , wherein the amplifier biasing circuit is adapted to be controlled by the control signals.

22. The circuital arrangement according to claim 20 , wherein the amplifier biasing circuit comprises a DC/DC converter or a low dropout (LDO) regulator configured to provide power to the respective one of the first amplifying circuit and the second amplifying circuit.

23. The circuital arrangement according to claim 22 , wherein the DC/DC converter or the LDO regulator is controlled according to one of: a) an envelope tracking scheme, and b) an average power tracking scheme.

24. The circuital arrangement according to claim 20 , wherein the amplifier biasing circuit comprises gate biasing circuits to bias transistors of the respective one of the first amplifying circuit and the second amplifying circuit.

25. The circuital arrangement according to claim 20 , wherein:

Assignees

• Peregrine Semiconductor Corp

Inventors

• Nobbe Dan William
• Reedy Ronald Eugene
• Bacon Peter
• Cable James S

Classifications

• H04B17/11

  for calibration · CPC title

• H03H7/38

  Impedance-matching networks · CPC title

• H03F1/0277

  Selecting one or more amplifiers from a plurality of amplifiers · CPC title

• H03F2200/456

  A scaled replica of a transistor being present in an amplifier · CPC title

• H03F2200/471

  the voltage being sensed · CPC title