Semiconductor device including volatile and non-volatile memory cells

Patent metadata

Field	Value
Publication number	US-10685708-B2
Application number	US-201816059317-A
Country	US
Kind code	B2
Filing date	Aug 9, 2018
Priority date	Feb 23, 2018
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

First claim

What is claimed is:

1. A semiconductor device comprising a substrate having a volatile memory region and a non-volatile memory region,
wherein the volatile memory region comprises:
a cell capacitor in the substrate; and
a cell transistor connected to the cell capacitor,

wherein the non-volatile memory region has a plurality of non-volatile memory cells at a higher level than an upper surface of the substrate, and the non-volatile memory region comprises:
a plurality of mold layers and a plurality of non-volatile gate electrodes alternately and repeatedly stacked on the substrate; and
a channel structure passing through the plurality of mold layers and the plurality of non-volatile gate electrodes,

wherein the volatile memory region and the non-volatile memory region are side by side, and
wherein the channel structure and the plurality of non-volatile gate electrodes constitute the plurality of non-volatile memory cells.

2. The semiconductor device of claim 1 ,
wherein the cell capacitor is at a lower level than the upper surface of the substrate.

3. The semiconductor device of claim 1 ,
wherein the cell capacitor comprises:
a first electrode in the substrate;
a second electrode facing the first electrode; and
a capacitor dielectric layer between the first electrode and the second electrode, and

wherein the second electrode is in a capacitor trench in the substrate.

4. The semiconductor device of claim 3 ,
wherein the capacitor trench is disposed from the upper surface of the substrate toward an inside of the substrate, and
wherein the capacitor trench has a height greater than a horizontal width.

5. The semiconductor device of claim 3 , wherein a lower surface of the first electrode is at a lower level than a bottom of the capacitor trench.

6. The semiconductor device of claim 3 ,
wherein the substrate comprises:
a first well adjacent to the upper surface of the substrate;
a second well at a lower level than that of the first well; and
a third well at a lower level than that of the second well,

wherein the second well is between the first well and the third well,
wherein the first well and the third well contain first conductive impurities, and
wherein the second well contains second conductive impurities different from the first conductive impurities.

7. The semiconductor device of claim 6 , wherein a lower surface of the first electrode is at substantially the same level as a lower surface of the second well.

8. The semiconductor device of claim 6 ,
wherein the first electrode comprises:
an inner electrode adjacent to the capacitor trench; and
an outer electrode surrounding an outer surface of the inner electrode, and

wherein the capacitor dielectric layer is between the inner electrode and the second electrode.

9. The semiconductor device of claim 8 , wherein the capacitor trench penetrates into the third well through the first well and the outer electrode.

10. The semiconductor device of claim 8 , wherein a lowermost end of the inner electrode is at a lower level than a lower surface of the outer electrode.

11. The semiconductor device of claim 8 , wherein a lowermost end of the inner electrode is at a lower level than an uppermost end of the third well.

12. The semiconductor device of claim 3 ,
wherein the cell transistor comprises:
a cell drain region;
a cell source region spaced apart from the cell drain region; and
a cell gate electrode between the cell drain region and the cell source region, and

wherein the cell drain region is connected to the second electrode.

13. The semiconductor device of claim 12 , wherein the cell gate electrode is in the substrate.

14. The semiconductor device of claim 12 , wherein an upper surface of the cell gate electrode is at a lower level than an upper end of the substrate.

15. The semiconductor device of claim 1 , wherein the channel structure comprises:
a core pattern;
a channel pattern surrounding the core pattern; and
an information storage pattern between the channel pattern and the plurality of non-volatile gate electrodes.

16. The semiconductor device of claim 1 ,
wherein the non-volatile memory region comprises:
a plurality of first wires parallel to one another on the substrate; and
a plurality of second wires parallel to one another and intersecting the plurality of first wires, and

wherein the plurality of non-volatile memory cells are at intersections of the plurality of first wires and the plurality of second wires.

17. The semiconductor device of claim 1 , further comprising a peripheral circuit region adjacent to the volatile memory region,
wherein the peripheral circuit region has a peripheral transistor on the substrate.

18. The semiconductor device of claim 17 , wherein the peripheral circuit region is between the volatile memory region and the non-volatile memory region.

19. A semiconductor device comprising:
a substrate;
a volatile memory cell in the substrate; and
a non-volatile memory cell on the substrate, the non-volatile memory cell comprising:
a plurality of mold layers and a plurality of non-volatile gate electrodes alternately and repeatedly stacked on the substrate; and
a channel structure passing through the plurality of mold layers and the plurality of non-volatile gate electrodes,

wherein the non-volatile memory cell is at a higher level than an upper surface of the substrate, and
wherein the channel structure and the plurality of non-volatile gate electrodes constitute the non-volatile memory cell.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Chang Hoon
• Shin Yoo Cheol
• Lim Jun Hee
• Baek Sung Kweon
• Lee Chan Ho
• Jang Won Chul
• Hwang Sun Gyung

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title

• H10D84/80 Primary

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title