Semiconductor device

Patent metadata

Field	Value
Publication number	US-10685695-B2
Application number	US-201916405219-A
Country	US
Kind code	B2
Filing date	May 7, 2019
Priority date	Jun 9, 2017
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate; and
a peripheral circuit region disposed outside of the memory cell region, and including low voltage transistors and high voltage transistors,
wherein the low voltage transistors have a channel length shorter than a channel length of the high voltage transistors, and
wherein the low voltage transistors include first transistors in which M layers are stacked vertically, and the high voltage transistors include second transistors in which N layers are stacked vertically, M being greater than N, wherein the M lavers have side surfaces substantially coplanar with one another, and the N layers have side surfaces substantially coplanar with one another.

2. The semiconductor device of claim 1 , wherein the first transistors include p-type transistors in which A layers are stacked vertically and n-type transistors in which B layers are stacked vertically, A being greater than B.

3. The semiconductor device of claim 1 , wherein the first transistors includes a first gate dielectric layer and a first gate electrode layer including C layers, and the second transistors include a second gate dielectric layer and a second gate electrode layer including D layers, and C is greater than D.

4. The semiconductor device of claim 1 , wherein the first transistors includes a first gate dielectric layer and a first gate electrode layer including a metal, and
herein the second transistors include a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

5. The semiconductor device of claim 4 , wherein the first gate electrode layer includes a first conductive layer including metal and a second conductive layer including polysilicon.

6. The semiconductor device of claim 4 , wherein the first transistors further include the. second gate dielectric layer disposed below the first gate dielectric layer.

7. The semiconductor device of claim 6 , wherein a thickness of the second gate dielectric layer in the second transistors is greater than a thickness of the second gate dielectric layer in the first transistors.

8. The semiconductor device of claim 4 , wherein the first transistors include n-type transistors and p-type transistors, the first gate electrode layer of the n-type, transistors includes a first metal layer, and the first gate electrode layer of the p-type transistors includes a second metal layer having a work function higher than a work function of the first metal layer.

9. The semiconductor device of claim 8 , wherein the first gate electrode layer of the p-type transistors further includes the first metal layer on the second metal layer.

10. The semiconductor device of claim 4 , wherein the first transistors include n-type transistors and p-type transistors, the first gate electrode layer includes a first conductive layer and a second conductive layer, and a thickness of at least one of the first conductive layer and the second conductive layer is different in the n-type transistors and the p-type transistors.

11. The semiconductor device of claim 4 , wherein the first transistors further include the second gate electrode layer stacked on the first gate electrode layer.

12. The semiconductor device of claim 1 , wherein the first transistors generate an electrical signal required for communications between the memory cells and an external host, and the second transistors generate an electrical signal required for operations of the memory cells.

13. The semiconductor device of claim 12 , wherein the first transistors are included in an input/output circuit.

14. The semiconductor device of claim 1 , wherein the low voltage transistors have an operating voltage of 1 V to 5 V, and the high voltage transistors have an operating voltage of 10 V to 40 V.

15. The semiconductor device of claim 1 , wherein the memory cells include:
a channel region disposed in the channel holes;
a cell gate dielectric layer including a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and
a cell gate electrode layer surrounding the channel holes.

16. A semiconductor device comprising:
a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate; and
a peripheral circuit region disposed outside of the memory cell region, and including first transistors and second transistors having a channel length longer than a channel length of the first transistors,
wherein the first transistors include a first gate dielectric layer and a first gate electrode layer, and the second transistors include a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer,
wherein the first gate electrode layer includes a first conductive layer including metal and a second conductive layer including polysilicon, and
wherein a thickness of the first gate dielectric law is in a rate of about 30 Å to about 90 Å, and a thickness of the second sate dielectric layer is in a range of about 300 Å to about 500 Å.

17. The semiconductor device of claim 16 , wherein the second gate electrode layer includes polysilicon.

18. The semiconductor device of claim 16 . wherein the first gate electrode layer further includes a third conductive layer including metal between the first conductive layer and the second conductive layer.

19. A semiconductor device comprising:
a memory cell region including memory cells including a charge storage layer; and
a peripheral circuit region disposed outside of the memory cell region, and including first transistors including a first gate dielectric layer including a high-k material and a first gate electrode layer, and second transistors including a second gate dielectric layer including silicon dioxide (SiO 2 ) and a second gate electrode layer including polysilicon,
wherein the first transistors include n-type transistors and p-type transistors, the first gate electrode layer of the p-type transistors includes a first metal layer and a second metal layer having a work function higher than a work function of the first metal layer.

20. The semiconductor device of claim 19 , wherein the first gate electrode layer of the n-type transistors includes the first metal layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Chang Hoon
• Kim Yong Seok
• Lim Jun Hee

Classifications

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D84/014

  the gate conductors having different materials or different implants · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title