Semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9893082-B2
Application number	US-201615250091-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Jan 30, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

First claim

What is claimed is:

1. A method of fabricating a semiconductor memory device, comprising:
forming a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a cell region of a substrate,
the substrate including the cell region, a peripheral region, and a boundary region between the cell region and the peripheral region;
forming a cell channel structure penetrating the stack on the cell region,
the cell channel structure including a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern,
the first channel pattern contacting the first semiconductor pattern,
the first semiconductor pattern extending to a first height from a surface of the substrate to a top surface of the first semiconductor pattern;

forming a mold insulating layer on the peripheral region and the boundary region; and
forming a first dummy channel structure penetrating the mold insulating layer on the boundary region,
the first dummy channel structure being spaced apart from the stack,
the first dummy channel structure including a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern,
the second channel pattern contacting the second semiconductor pattern,
the second semiconductor pattern extending to a second height from the surface of the substrate to a top surface of the second semiconductor pattern, and
the first height being greater than the second height.

2. The method of claim 1 , wherein the forming a cell channel structure includes forming a first data storing pattern between the stack and the first channel pattern.

3. The method of claim 2 , wherein
the forming a first dummy channel structure includes forming a second data storing pattern between the mold insulating layer and the second channel pattern,
the first channel pattern and the second channel pattern include a same channel material,
the first data storing pattern and the second data storing pattern include a same data storing material.

4. The method of claim 1 , wherein
the cell region includes a cell array region and a connection region adjacent to the cell array region,
the stack includes an edge part with a stepwise structure on the connection region, and
the mold insulating layer covers the edge part of the stack.

5. The method of claim 4 , further comprising:
forming a second dummy channel structure penetrating the edge part of the stack on the connection region,
wherein the forming the second dummy channel structure includes forming a third semiconductor pattern in contact with the substrate and a third channel pattern on the third semiconductor pattern.

6. The method of claim 1 , further comprising:
forming a peripheral circuit device on the peripheral region,
wherein the forming a peripheral circuit device includes forming a peripheral gate insulating layer and a peripheral gate electrode stacked on the substrate and source/drain regions in the substrate adjacent to sidewalls of the peripheral gate electrode.

7. The method of claim 1 , further comprising:
forming a gate dielectric layer contacting a sidewall of the first semiconductor pattern,
wherein the gate dielectric layer is not formed adjacent to a sidewall of the second semiconductor pattern.

8. A method of fabricating a semiconductor memory device, the method comprising:
forming a mold structure on a cell region of a substrate,
the mold structure including insulating layers and sacrificial layers that are alternately and repeatedly stacked on the cell region,
the substrate including the cell region, a peripheral region, and a boundary region between the cell region and the peripheral region,
the cell region including a cell array region and a connection region;

forming a mold insulating layer on the connection region, the boundary region, and the peripheral region, the mold insulating layer covering a portion of the mold structure;
forming a cell channel structure penetrating the mold structure on the cell region,
the cell channel structure including a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern,
the first channel pattern contacting the first semiconductor pattern;

forming first dummy channel structures penetrating the mold insulating layer and the mold structure on the connection region,
each of the first dummy channel structures including a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern,
the second channel pattern contacting the second semiconductor pattern; and
forming a second dummy channel structure penetrating the mold insulating layer on the boundary region,
the second dummy channel structure including a third semiconductor pattern contacting the substrate and a third channel pattern on the third semiconductor pattern,
the third channel pattern contacting the third semiconductor pattern; and
forming gate electrodes, wherein the forming gate electrodes includes forming a trench penetrating the mold structure, forming openings by selectively removing the sacrificial layers of the mold structure exposed by the trench, forming a gate conductive layer in the openings, and patterning the gate conductive layer.

9. The method of claim 8 , wherein
the first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern,
the second semiconductor pattern of at least one of the first dummy channel structures adjacent to the third semiconductor pattern further includes a first sub-semiconductor pattern,
the first sub-semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the first sub-semiconductor pattern,
the third semiconductor pattern extends to a third height from the surface of the substrate to a top surface of the third semiconductor pattern,
the second height is smaller than the first height, and
the third height is smaller than the first height.

10. The method of claim 9 , wherein
the second semiconductor pattern of at least one of the first dummy channel structures adjacent to the first semiconductor pattern further includes a second sub-semiconductor pattern,
the second sub-semiconductor pattern extends to a fourth height from the surface of the substrate to a top surface of the second sub-semiconductor pattern, and
the fourth height is greater than the second and third heights.

11. The method of claim 8 , wherein
the forming a cell channel structure further includes forming a first data storing pattern in contact with a sidewall of the first channel pattern,
the forming first dummy channel structures further includes forming second data storing patterns in contact with sidewalls of the second channel patterns,
the forming a second dummy channel structure further includes forming a third data storing pattern in contact with a sidewall of the third channel pattern,
the first, second, and third channel patterns are formed of a same channel material and
the first, second, and third data storing patterns are formed of a same data storing material.

12. The method of claim 8 , further comprising:
forming a plurality of second dummy channel structures, wherein
the forming a plurality of second dummy channel structures includes the forming a second dummy channel structure, and
the forming a plurality of second dummy channel structures includes forming the plurality of second dummy channel structures arranged in a direction, and
the forming a plurality of second dumm

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Chaeho
• Yang Sangryol
• Lee Woong
• Lim Seunghyun

Classifications

• H01L27/11573

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L29/42348

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic