Metrology using overlay and yield critical patterns

Patent metadata

Field	Value
Publication number	US-10685165-B2
Application number	US-201615082152-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	Jul 13, 2014
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

Metrology methods are provided, which comprise identifying overlay critical patterns in a device design, the overlay critical patterns having an overlay sensitivity to process variation above a specified threshold that depends on design specifications; and using metrology targets that correspond to the identified overlay critical patterns. Alternatively or complementarily, metrology methods comprise identifying yield critical patterns according to a corresponding process window narrowing due to specified process variation, wherein the narrowing is defined by a dependency of edge placement errors (EPEs) of the patterns on process parameters. Corresponding targets and measurements are provided.

First claim

What is claimed is:

1. A computer implementable method of designing a circuit device, the method executable on a computer including a central processing unit (CPU) capable of executing computer readable instructions stored on a non-transitory computer readable storage medium, which instructions, when read by the CPU, cause the CPU to perform operations comprising:
on a metrology target of a simulated circuit device, identifying at least one simulated circuit device pattern having an increased potential of producing a higher incidence of unacceptable devices as compared to one or more simulated circuit patterns identified as producing acceptable devices based on at least one specified process variation, which at least one specified process variation narrows a range of acceptable production deviations,
wherein the narrowing of the range of acceptable production deviations is based on an edge placement error of the simulated circuit device pattern and at least one process parameter.

2. The computer implementable method of claim 1 , wherein the CPU performs operations further comprising estimating the range of acceptable production deviations due to an effect of the at least one specified process variation/inaccuracy (PV) on the at least one simulated circuit device pattern that has the increased potential of producing the higher incidence of unacceptable devices.

3. The computer implementable method of claim 1 , wherein the CPU performs operations further comprising modifying the at least one process parameter to modify the range of acceptable production deviations.

4. The computer implementable method of claim 1 , wherein the CPU performs operations further comprising associating the identified at least one simulated circuit device pattern that has the increased potential of producing the higher incidence of unacceptable devices according to its effect on the range of acceptable production deviations.

5. The computer implementable method of claim 4 , wherein the CPU performs operations further comprising correcting for the range of acceptable production deviations, commonly for an associated at least one simulated circuit device pattern that has the increased potential of producing the higher incidence of unacceptable devices.

6. The computer implementable method of claim 5 , wherein the CPU performs operations further comprising splitting a cut mask to associate production of the associated at least one simulated circuit device pattern that has the increased potential of producing the higher incidence of unacceptable devices.

Assignees

• Kla Tencor Corp

Inventors

• Kandel Daniel
• Smith Mark D
• Wagner Mark
• Amit Eran
• Lee Myungjun

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27 Primary

  Structural arrangements therefor · CPC title

• Y02P80/30

  Reducing waste in manufacturing processes; Calculations of released waste quantities · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title