Power-saving current-mode digital-to-analog converter (DAC)

Patent metadata

Field	Value
Publication number	US-10680640-B2
Application number	US-201615386213-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Dec 21, 2016
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A digital-to-analog converter (DAC) for an audio system in a media device, such as a portable media device or smart phone, may be operated to turn off portions of the DAC to reduce power consumption. Segments of a segment-able DAC may be powered off when the output level of the DAC is lower than the full scale output of the DAC. For example, DAC elements within a finite impulse response (FIR) DAC may be turned off when a desired output level can be obtained with less than all DAC elements of the FIR DAC.

First claim

What is claimed is:

1. A method of operating a finite impulse response (FIR) digital-to-analog converter (DAC) with two or more DAC segments, comprising:
buffering the input signal to obtain a buffered input signal;
determining a first portion of the two or more DAC segments sufficient to generate an output signal based, at least in part, on an envelope of the buffered input signal; and
powering off a second portion of the two or more DAC segments not in the first portion of the two or more DAC segments.

2. The method of claim 1 , further comprising:
powering on the second portion of the two or more DAC segments; and
repeating the steps of determining the first portion and powering off the second portion, wherein the repeating of the steps of determining the first portion and powering off the second portion dynamically controls a power output of the FIR DAC during playback of media.

3. The method of claim 1 , wherein the step of determining the first portion of the two or more DAC segments is based, at least in part, on a transient envelope of the buffered input signal.

4. The method of claim 1 , wherein the step of powering off the second portion of the two or more DAC segments comprises:
powering off a first fraction of a plurality of elements within the second portion of the two or more DAC segments; and
powering off a second fraction of the plurality of elements within the second portion of the two or more DAC segments after powering off the first fraction.

5. The method of claim 1 , wherein the step of powering off the second portion of the two or more DAC segments comprises providing a dump code to the second portion of the two or more DAC segments.

6. The method of claim 5 , wherein the step of powering off the second portion of the two or more DAC segments comprises:
shunting output to ground from switch elements of the second portion of the two or more DAC segments in response to the dump code; and
disconnecting a power supply from the switch elements shunted to ground.

7. The method of claim 6 , wherein the step of powering down the second portion of the two or more DAC segments comprises:
reducing a clock rate of at least some switch elements of the second portion of the two or more DAC segments in response to the dump code.

8. The method of claim 5 , wherein the step of powering off the second portion of the two or more DAC segments comprises applying a step input to the first portion of the two or more DAC segments, wherein the step input is opposite of a calibrated offset of the second portion of the two or more DAC segments.

9. The method of claim 5 , further comprising calibrating the second portion of the two or more DAC segments after the second portion is powered off.

10. The method of claim 9 , further comprising:
powering on the second portion of the two or more DAC segments;
after powering on the second portion of the two or more DAC segments, determining a third portion of the two or more DAC segments sufficient to generate the output signal based, at least in part, on a second envelope of the buffered input signal;
after determining the third portion, powering off a fourth portion of the two or more DAC segments; and
after powering off the fourth portion of the two or more DAC segments, calibrating the fourth portion of the two or more DAC segments, wherein the fourth portion is different from the second portion.

11. The method of claim 1 , wherein the step of powering off the second portion of the two or more DAC segments comprises providing a zero code to the second portion of the two or more DAC segments.

12. The method of claim 11 , wherein the step of powering off the second portion of the two or more DAC segments comprises:
modulating switch elements of the second portion of the two or more DAC segments between ground and an output node in response to the zero code; and
disconnecting a power supply from the switch elements.

13. The method of claim 1 , wherein the step of powering off the second portion of the two or more DAC segments comprises powering off a plurality of cascade switch within the second portion of the two or more DAC segments.

14. The method of claim 1 , wherein the step of powering off the second portion of the two or more DAC segments comprises switch off a plurality of mirror switches within the second portion of the two or more DAC segments.

15. The method of claim 1 , wherein the buffered input signal comprises a high fidelity audio signal.

16. A finite impulse response (FIR) digital-to-analog converter (DAC), comprising:
two or more DAC segments;
a buffer coupled to the input node, wherein the buffer is configured to buffer an input signal to obtain a buffered input signal;
a controller coupled to the two or more DAC segments and configured to perform steps comprising:
determining a first portion of the two or more DAC segments sufficient to generate an output signal based, at least in part, on an envelope of the buffered input signal; and
powering off a second portion of the two or more DAC segments not in the first portion of the two or more DAC segments.

17. The apparatus of claim 16 , wherein the controller is further configured to perform steps comprising:
powering on the second portion of the two or more DAC segments; and
repeating the steps of determining the first portion and powering off the second portion,
wherein the repeating of the steps of determining the first portion and powering off the second portion dynamically controls a power output of the FIR DAC during playback of media.

18. The apparatus of claim 16 , wherein the step of determining the first portion of the two or more DAC segments is based, at least in part, on a transient envelope of the buffered input signal.

19. The apparatus of claim 16 , wherein the step of powering off the second portion of the two or more DAC segments comprises:
powering off a first fraction of a plurality of elements within the second portion of the two or more DAC segments; and
powering off a second fraction of the plurality of elements within the second portion of the two or more DAC segments after powering off the first fraction.

20. The apparatus of claim 16 , wherein the step of powering off the second portion of the two or more DAC segments comprises providing a dump code to the second portion of the two or more DAC segments.

21. The apparatus of claim 20 , wherein the step of powering off the second portion of the two or more DAC segments comprises:
shunting output to ground from switch elements of the second portion of the two or more DAC segments in response to the dump code; and
disconnecting a power supply from the switch elements shunted to ground.

22. The apparatus of claim 21 , wherein the step of powering down the second portion of the two or more DAC segments comprises:
reducing a clock rate of at least some switch elements of the second portion of the two or more DAC segments in response to the dump code.

23. The apparatus of claim 20 , wherein the step of powering off the second portion of the two or more DAC segments comprises applying a step input to the first portion of the two or more DAC segments, wherein the step input is opposite of a calibrated offset of the second portion of the two or more DAC segments.

24. The apparatus of claim 20 , wherein the controller is configured to perform steps comprising calibrating the second portion of the two or more DAC segments aft

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Peterson Cory J
• Ilango Anand

Classifications

• H03M1/742

  using current sources as quantisation value generators · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H04R3/007

  Protection circuits for transducers · CPC title

• H03M3/504 Primary

  the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title