Switchable secondary playback path

Patent metadata

Field	Value
Publication number	US-9680488-B2
Application number	US-201615050857-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	Apr 14, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.

First claim

What is claimed is:

1. A processing system comprising:
a plurality of processing paths including a first processing path and a second processing path, wherein:
the first processing path comprises a first digital-to-analog converter for converting an entirety of a digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state; and
the second processing path comprises a second digital-to-analog converter for converting at least a portion of the entirety of the digital input signal into a second intermediate analog signal; and

an output stage configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal.

2. The processing system of claim 1 , wherein the second digital-to-analog converter when converting the digital input signal into the second intermediate analog signal consumes lesser power than the first digital-to-analog converter when converting the digital input signal into the first intermediate analog signal.

3. The processing system of claim 1 , wherein the first digital-to-analog converter introduces lesser noise into the first processing path relative to noise introduced by the second digital-to-analog converter into the second processing path.

4. The processing system of claim 1 , wherein the second digital-to-analog converter comprises a resistor ladder comprising a plurality of resistors each coupled to each other at respective first terminals and each coupled at their respective second terminals to a corresponding driver driving a signal indicative of a value of a single bit of the digital input signal.

5. The processing system of claim 1 , further comprising a controller configured to operate the first digital-to-analog converter in the low-power state when a magnitude of the digital input signal is below a threshold magnitude.

6. The processing system of claim 5 , wherein the controller is further configured to, when the magnitude of the digital input signal is below the threshold magnitude, cause the first processing path to output the first intermediate analog signal having an approximately zero magnitude.

7. The processing system of claim 6 , wherein the controller is further configured to, when the magnitude of the digital input signal is above the threshold magnitude, cause the second processing path to output the second intermediate analog signal having an approximately zero magnitude.

8. The processing system of claim 5 , wherein:
the first processing path comprises a first gain element configured to apply a first gain to the first processing path;
the second processing path comprises a second gain element configured to apply a second gain to the second processing path; and
the controller is further configured to vary the first gain and the second gain based on the magnitude of the digital input signal, such that the sum of the first gain and the second gain remains substantially constant as the magnitude of the digital input signal varies.

9. The processing system of claim 8 , wherein the controller is further configured to vary the first gain and the second gain such that, when the magnitude of the digital input signal is above the threshold magnitude:
the first gain increases as the magnitude of the digital input signal increases and vice versa; and
the second gain increases as the magnitude of the digital input signal decreases and vice versa.

10. The processing system of claim 5 , wherein for magnitudes of the digital input signal above the threshold magnitude, noise introduced by the second digital-to-analog converter is at least partially cancelled by the first digital-to-analog converter.

11. The processing system of claim 5 , wherein the controller is further configured to:
when the magnitude of the digital input signal is above the threshold magnitude, cause the first processing path and second processing path to both process the digital input signal to generate the analog signal; and
when the magnitude of the digital input signal is below the threshold magnitude, cause the second processing path to fully process the digital input signal.

12. The processing system of claim 11 , wherein the controller is further configured to, when the magnitude of the digital input signal is above the threshold magnitude:
cause the first processing path to process components of the digital input signal below a particular frequency; and
cause the second processing path to process components of the digital input signal above the particular frequency.

13. The processing system of claim 1 , further comprising a multi-stage noise shaping structure, wherein the first processing path includes a first stage of the multi-stage noise-shaping structure and the second processing path includes a second stage of the multi-stage noise-shaping structure.

14. The processing system of claim 13 , further comprising a controller configured to operate the first digital-to-analog converter in the low-power state when a magnitude of the digital input signal is below a threshold magnitude.

15. The processing system of claim 14 , wherein the controller is further configured to, when the magnitude of the digital input signal is below the threshold magnitude, cause the first processing path to output the first intermediate analog signal having an approximately zero magnitude.

16. The processing system of claim 15 , wherein the controller is further configured to, when the magnitude of the digital input signal is below the threshold magnitude, cause the first stage of the multi-stage noise-shaping structure to operate in a low power mode.

17. The processing system of claim 15 , wherein the controller is further configured to:
when the magnitude of the digital input signal is above the threshold magnitude, cause the first processing path and second processing path to both process the digital input signal to generate the analog signal; and
when the magnitude of the digital input signal is below the threshold magnitude, cause the second processing path to fully process the digital input signal.

18. A method comprising:
generating a first intermediate analog signal with a first processing path comprising a first digital-to-analog converter for converting an entirety of a digital input signal into the first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state;
generating a second intermediate analog signal with a second processing path comprising a second digital-to-analog converter for converting at least a portion of the entirety of the digital input signal into the second intermediate analog signal;
generating an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal.

19. The method of claim 18 , wherein the second digital-to-analog converter when converting the digital input signal into the second intermediate analog signal consumes lesser power than the first digital-to-analog converter when converting the digital input signal into the first intermediate analog signal.

20. The method of claim 18 , wherein the first digital-to-analog converter introduces lesser noise into the first processing path relative to noise introduced by the second digital-to-analog converter into the second processing path.

21. The method of claim 18 , wherein the second digital-to-analog converter comprises a

Assignees

• Cirrus Logic Inc

Inventors

• Das Tejasvi
• Melanson John L
• Tucker John C
• Fei Xiaofan

Classifications

• H03M1/70

  Automatic control for modifying converter range · CPC title

• H03M3/32

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M3/414

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title

• H03M3/416

  all these quantisers being multiple bit quantisers · CPC title