Offset insensitive quadrature clock error correction and duty cycle calibration for high-speed clocking

Patent metadata

Field	Value
Publication number	US-9602082-B2
Application number	US-201514814401-A
Country	US
Kind code	B2
Filing date	Jul 30, 2015
Priority date	Jul 30, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit. A digital value is used by a feedback algorithm to correct the clock distortion.

First claim

What is claimed is:

1. A distortion detection unit for detecting distortion of a clock signal, comprising:
a duty cycle distortion detection unit;
a quadrature clock error detection unit; and
one or more sampling capacitors coupled to the duty cycle distortion detection unit and the quadrature clock error detection unit,
wherein the duty cycle distortion detection unit and the quadrature clock error detection unit are operable to provide device mismatch-related voltages to the one or more sampling capacitors to charge the one or more sampling capacitors for mismatch correction,
wherein the duty cycle distortion detection unit is operable to output a first differential value via the one or more sampling capacitors to indicate a duty cycle distortion polarity of the clock signal, and
wherein the quadrature clock error detection unit is operable to output a second differential value via the one or more sampling capacitors to indicate a quadrature clock error polarity of the clock signal.

2. The distortion detection unit of claim 1 , further comprising:
one or more differential amplifiers operable to amplify the first and second differential values to generate a first amplified differential value and a second amplified differential value.

3. The distortion detection unit of claim 1 , further comprising:
a differential latch operable to store a bit based on the first differential value.

4. The distortion detection unit of claim 1 , wherein:
the quadrature clock error detection unit includes a plurality of transistors configured into a plurality of exclusive OR (“XOR”) gates operable to detect quadrature clock error in the clock signal.

5. The distortion detection unit of claim 4 , wherein the plurality of transistors are configured in a symmetric configuration.

6. The distortion detection unit of claim 4 , wherein the quadrature clock error detection unit further comprises:
a plurality of switches configured to apply a set of ideal clock voltages to the plurality of transistors to generate a device mismatch-related voltage of the device mismatch-related voltages.

7. The distortion detection unit of claim 4 , wherein the quadrature clock error detection unit further comprises:
a plurality of switches configured to apply the clock signal to the plurality of transistors to generate the first differential value.

8. The distortion detection unit of claim 1 , wherein:
the clock signal includes an in-phase clock signal, an inverted in-phase clock signal, a quadrature-phase clock signal, and an inverted quadrature-phase clock signal.

9. The distortion detection unit of claim 1 , wherein:
the duty cycle distortion detection unit includes a set of resistors coupled to the clock signal and to the sampling capacitors and operable to generate a differential signal based on duty cycle distortion of the clock signal.

10. A distortion correction system for correcting distortion of a clock signal, the distortion correction system comprising:
a distortion detection unit operable to detect duty cycle distortion and quadrature clock error distortion;
a clock calibration unit operable to generate a duty cycle distortion correction control signal based on a first output from the distortion detection unit and to generate a quadrature clock error correction control signal based on a second output from the distortion detection unit;
a duty cycle distortion correction unit operable to correct distortion of the clock signal based on the duty cycle distortion correction control signal and based on the quadrature clock error correction control signal,
wherein the distortion detection unit comprises:
a duty cycle distortion detection unit;
a quadrature clock error detection unit; and
one or more sampling capacitors coupled to the duty cycle distortion detection unit and the quadrature clock error detection unit,
wherein the duty cycle distortion detection unit and the quadrature clock error detection unit are operable to provide device mismatch-related voltages to the one or more sampling capacitors to charge the one or more sampling capacitors for mismatch correction,
wherein the duty cycle distortion detection unit is operable to output a first differential value via the one or more sampling capacitors to indicate a duty cycle distortion polarity of the clock signal, and
wherein the quadrature clock error detection unit is operable to output a second differential value via the one or more sampling capacitors to indicate a quadrature clock error polarity of the clock signal.

11. The distortion correction system of claim 10 , wherein the distortion detection unit further comprises:
one or more differential amplifiers operable to amplify the first and second differential values to generate a first amplified differential value and a second amplified differential value.

12. The distortion correction system of claim 10 , wherein the distortion detection unit further comprises:
a differential latch operable to store a bit based on the first differential value.

13. The distortion correction system of claim 10 , wherein:
the quadrature clock error detection unit includes a plurality of transistors configured into a plurality of exclusive OR (“XOR”) gates operable to detect quadrature clock error in the clock signal.

14. The distortion correction system of claim 13 , wherein the plurality of transistors are configured in a symmetric configuration.

15. The distortion correction system of claim 13 , wherein the quadrature clock error detection unit further comprises:
a plurality of switches configured to apply a set of ideal clock voltages to the plurality of transistors to generate a device mismatch-related voltage of the device mismatch-related voltages.

16. The distortion correction system of claim 13 , wherein the quadrature clock error detection unit further comprises:
a plurality of switches configured to apply the clock signal to the plurality of transistors to generate the first differential value.

17. The distortion correction system of claim 10 , wherein:
the clock signal includes an in-phase clock signal, an inverted in-phase clock signal, a quadrature-phase clock signal, and an inverted quadrature-phase clock signal.

18. The distortion correction system of claim 10 , wherein:
the duty cycle distortion detection unit includes a set of resistors coupled to the clock signal and to the sampling capacitors and operable to generate a differential signal based on duty cycle distortion of the clock signal.

19. A method for correcting distortion of a clock signal, the method comprising:
providing device mismatch-related voltages to one or more sampling capacitors to charge the one or more sampling capacitors for mismatch correction;
outputting a first differential value via the one or more sampling capacitors to indicate a duty cycle distortion polarity of the clock signal; and
outputting a second differential value via the one or more sampling capacitors to indicate a quadrature clock error polarity of the clock signal.

20. The method of claim 19 , wherein outputting the first differential value comprises:
detecting quadrature clock error in the clock signal via a plurality of transistors configured into a plurality of exclusive OR (“XOR”) gates.

Assignees

• Xilinx Inc

Inventors

• Hedayati Hiva
• Frans Yohan

Classifications

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• G06F1/04 Primary

  Generating or distributing clock signals or signals derived directly therefrom · CPC title