Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit

Patent metadata

Field	Value
Publication number	US-10680105-B2
Application number	US-201715464943-A
Country	US
Kind code	B2
Filing date	Mar 21, 2017
Priority date	Mar 21, 2017
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

First claim

What is claimed is:

1. A method of fabricating a symmetric element of a resistive processing unit (RPU), the method comprising:
forming a substrate with a channel region connecting two doped regions;
forming a source above one of the two doped regions and a drain above another of the two doped regions, wherein the forming the source and the drain includes forming the source and the drain to be entirely above the channel region that connects the two doped regions;
forming a gate above the channel region;
disposing a bar ferroelectric above the channel region and below the gate; and
forming a first electrode between the source and the gate and forming a second electrode between the drain and the gate, wherein the forming the first electrode and the second electrode includes forming the first electrode and the second electrode to be entirely above the bar ferroelectric.

2. The method according to claim 1 , wherein forming the source and the drain includes forming the source and the drain on opposite sides of the bar ferroelectric.

3. The method according to claim 1 , further comprising forming an insulating layer on the channel region.

4. The method according to claim 3 , wherein the disposing the bar ferroelectric includes disposing the bar ferroelectric above the insulating layer such that the bar ferroelectric is separated from the channel region by the insulating layer.

5. The method according to claim 1 , further comprising forming an insulating layer on the channel region.

6. The method according to claim 5 , wherein the disposing the bar ferroelectric includes disposing the bar ferroelectric above the insulating layer such that the first electrode and the second electrode are formed above the insulating layer.

Assignees

• IBM

Inventors

• Han Jin-Ping
• Muralidhar Ramachandran
• Newns Dennis M
• Solomon Paul M

Classifications

• H01L27/1159

  Electricity · mapped topic

• H01L29/78391 Primary

  Electricity · mapped topic

• H01L29/40111

  Electricity · mapped topic

• H01L29/6684

  Electricity · mapped topic

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title