Semiconductor device comprising work function metal pattern in boundary region and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10679997-B2
Application number	US-201916391888-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Feb 8, 2017
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
providing a substrate including a cell region and a core region, the core region including first and second regions;
forming a boundary element isolation layer in the substrate between the cell region and the core region;
forming a high-k dielectric layer on the substrate;
forming a first work function metal layer on the high-k dielectric layer;
forming a first photoresist on the first work function metal layer, the first photoresist overlapping at least a part of the boundary element isolation layer and the first region and not overlapping the second region;
patterning the first work function metal layer using the first photoresist as an etch mask;
forming a second work function metal layer on the substrate and the patterned first work function metal layer;
forming a second photoresist on the second work function metal layer, the second photoresist overlapping at least a part of the boundary element isolation and the first and second regions and not overlapping the cell region; and
patterning the second work function metal layer and the high-k dielectric layer using the second photoresist as an etch mask.

2. The method for fabricating the semiconductor device of claim 1 , wherein a first length of the first photoresist overlapping the boundary element isolation layer is different from a second length of the second photoresist overlapping the boundary element isolation layer.

3. The method for fabricating the semiconductor device of claim 2 , wherein the first length is shorter than the second length.

4. The method for fabricating the semiconductor device of claim 2 , wherein the first length is longer than the second length.

5. The method for fabricating the semiconductor device of claim 1 , wherein a first length of the first photoresist overlapping the boundary element isolation layer is substantially the same with a second length of the second photoresist overlapping the boundary element isolation layer.

6. The method for fabricating the semiconductor device of claim 1 , further comprising:
etching a part of an upper portion of the boundary element isolation layer exposed by the patterned second work function metal layer and the patterned high-k dielectric layer.

7. The method for fabricating the semiconductor device of claim 1 , wherein the first work function metal layer includes at least one of tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tantalum carbide (TaC), and
the second work function metal layer includes at least one of lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb) and titanium nitride (TiN).

8. A method for fabricating a semiconductor device, the method comprising:
providing a substrate including a cell region, a core region, and a boundary region between the cell region and the core region;
forming a boundary element isolation layer in the substrate of the boundary region, the boundary element isolation layer separating the cell region from the core region;
forming a high-k dielectric layer on at least a part of the boundary element isolation layer and the substrate of the core region;
forming a first work function metal pattern including a first extension that extends beyond a first edge of the boundary element isolation layer and overlaps the boundary element isolation layer, the first work function metal pattern being on the high-k dielectric layer; and
forming a second work function metal pattern including a second extension that extends beyond the first edge of the boundary element isolation layer and overlaps the boundary element isolation layer, a portion of one of the first work function metal pattern and the second work function metal pattern being on the other of the first work function metal pattern and the second work function metal pattern on the boundary element isolation layer, and an end of the second extension extending in a direction from the core region towards the cell region overlapping the boundary element isolation layer,
wherein a first length of the first extension between an outer edge of the first work function metal pattern and the first edge of the boundary element isolation layer in a horizontal direction parallel to a top surface of the substrate and extending in the direction from the core region toward the cell region is different from a second length of the second extension between an outer edge of the second work function metal pattern and the first edge of the boundary element isolation layer in the horizontal direction parallel to the top surface of the substrate and extending in the direction from the core region toward the cell region.

9. The method for fabricating the semiconductor device of claim 8 , wherein the first length is shorter than the second length.

10. The method for fabricating the semiconductor device of claim 9 , wherein the high-k dielectric layer includes a third extension which overlaps the boundary element isolation layer, and
a third length of the third extension extending in the direction from the core region toward the cell region is substantially the same as the second length.

11. The method for fabricating the semiconductor device of claim 9 , wherein the boundary element isolation layer includes a recess adjacent to the second extension.

12. The method for fabricating the semiconductor device of claim 8 , wherein the first length is longer than the second length.

13. The method for fabricating the semiconductor device of claim 12 , wherein the high-k dielectric layer includes a third extension overlapping the boundary element isolation layer, and
a third length of the third extension extending in the direction from the core region toward the cell region is substantially the same as the first length.

14. The method for fabricating the semiconductor device of claim 12 , wherein the boundary element isolation layer includes a recess adjacent to the first extension.

15. The method for fabricating the semiconductor device of claim 8 , wherein the core region comprises first and second regions,
the first work function metal pattern is on the high-k dielectric layer of the first region, and is not on the substrate of the second region, and
the second work function metal pattern is on the first work function metal pattern of the first region, and is on the high-k dielectric layer of the second region.

16. The method for fabricating the semiconductor device of claim 11 , further comprising:
forming a sidewall of a longer one from among the first extension and the second extension, wherein the sidewall is aligned with an edge of the recess.

17. The method for fabricating the semiconductor device of claim 11 , wherein the forming the second work function metal pattern forms the second work function metal pattern such that a sidewall of the second extension is aligned with and edge of the recess.

18. The method for fabricating the semiconductor device of claim 14 , wherein the forming the first work function metal pattern forms the first work function metal pattern such that a sidewall of the first extension is aligned with an edge of the recess.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Ki Wook
• Kim Dong Oh
• Park Seok Han
• Yoon Chan Sic
• Lee Ki Seok
• Lee Ho In
• Jang Ju Yeon
• Park Je Min
• Hong Jin Woo

Classifications

• H01L29/1029

  Electricity · mapped topic

• H01L27/10894

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic

• H01L27/10852

  Electricity · mapped topic