Semiconductor device including capacitor and double-layer metal contact and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9318495-B2
Application number	US-201414489880-A
Country	US
Kind code	B2
Filing date	Sep 18, 2014
Priority date	Feb 14, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Disclosed are a semiconductor device comprising a capacitor and a double-layer metal contact and a method fabricating the same. The method comprising: forming a gate of a peripheral transistor for a peripheral circuit; forming a first contact and a first peripheral circuit wiring layer pattern on a first interlayer insulating layer; forming a second contact and a second peripheral circuit wiring layer pattern; selectively removing a portion of the second interlayer insulating layer in a cell region; forming a mold layer covering the second peripheral circuit wiring layer pattern; forming storage nodes passing through the mold layer; removing the mold layer; forming a dielectric layer and a plate node, which cover the storage nodes; forming a third interlayer insulating layer; and forming third contacts passing through the third interlayer insulating layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device comprising a capacitor and a double-layer metal contact, the method comprising:
forming a gate of a peripheral transistor for a peripheral circuit over a peripheral region of a semiconductor substrate including a cell region and the peripheral region;
forming a first interlayer insulating layer covering the gate;
forming a first contact and a first peripheral circuit wiring layer pattern, which are connected to the gate so as to constitute the peripheral circuit;
forming a second interlayer insulating layer over the first interlayer insulating layer to cover the first peripheral circuit wiring layer pattern,
wherein the second interlayer insulating layer includes a first portion and a second portion, and
wherein the first portion of the second interlayer insulating layer is disposed in the cell region and the second portion of the second interlayer insulating layer is disposed in the peripheral region;
forming a second peripheral circuit wiring layer pattern on the second portion of the second insulating layer and forming a second contact passing through the second interlayer insulating layer so as to constitute the peripheral circuit;
forming a mask pattern exposing the first portion of the second interlayer insulating layer with covering the second portion of the second interlayer insulating layer;
selectively removing the exposed whole first portion of the second interlayer insulating layer with remaining the second portion of the second interlayer insulating layer,
wherein a portion of the first insulating layer in the cell region is exposed by the remaining second portion of the second interlayer insulating layer;
forming an etch stopper over the exposed portion of the first insulating layer with extending to cover the remaining second portion of the second interlayer insulating layer;
forming a mold layer on the etch stopper;
forming storage nodes that pass through a portion of the mold layer in the cell region;
selectively removing the mold layer to expose the storage nodes while the etch stopper protects the second portion of the second interlayer insulating layer from the removing;
forming a dielectric layer and a plate node, which cover the exposed storage nodes;
forming a third interlayer insulating layer covering the plate node; and
forming third contacts that pass through the third interlayer insulating layer so as to be connected to the plate node and the second peripheral circuit wiring layer pattern, respectively.

2. The method of claim 1 , wherein the peripheral circuit comprises a sense amplifier that senses data to be stored in the storage nodes.

3. The method of claim 1 , wherein the method further comprises:
forming bit lines which are insulated by a portion of the first interlayer insulating layer on the cell region; and
forming storage node contacts which pass through the first interlayer insulating layer so as to be connected to the storage nodes, respectively.

4. The method of claim 3 , wherein forming the bit lines comprises:
forming damascene trenches in the first interlayer insulating layer; and
forming the bit lines filling the damascene trenches.

5. The method of claim 1 , wherein forming the first peripheral circuit wiring layer pattern comprises:
obtaining a layout of the peripheral circuit wiring line for the peripheral circuit;
extracting a layout of the first peripheral circuit wiring layer pattern, a layout of the second contact and a layout of the second peripheral circuit from the layout of the peripheral circuit wiring line;
forming a first contact hole exposing the gate; forming the first peripheral circuit wiring layer, which fills the first contact hole, on the first interlayer insulating layer; and
selectively etching the first circuit wiring layer so as to have a configuration corresponding to the layout of the first peripheral circuit wiring layer pattern, thus forming the first contact and the first peripheral circuit wiring layer pattern.

6. The method of claim 1 , wherein forming the second peripheral circuit wiring layer pattern comprises:
forming a second contact hole, which passes through the second interlayer insulating layer, so as to have a configuration corresponding to the layout of the second contact;
forming a second peripheral circuit wiring layer, which fills the second contact hole, on the second interlayer insulating layer; and
selectively etching the second peripheral circuit wiring layer so as to have a configuration corresponding to the layout of the second peripheral circuit wiring layer pattern, thus forming the second contact and the second peripheral circuit wiring layer pattern.

7. The method of claim 1 , wherein the forming the dielectric layer and the plate node comprises:
forming layers for the dielectric layer and the plate node so as to extend onto the etch stopper exposed by removal of the mold layer; and
selectively etching out a portion of the dielectric layer for the plate node, which overlaps with the remaining portion of the second interlayer insulating layer, thus patterning the plate node,
in which the third contacts which are connected to the plate node are located on the remaining portion of the second interlayer insulating portion.

8. The method of claim 1 , wherein the method further comprises: forming on the mold layer a support layer for supporting the storage nodes.

Assignees

• Sk Hynix Inc

Inventors

• Kang Chun Soo

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10B12/09 Primary

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H01L28/91

  Electricity · mapped topic