Semiconductor device

Patent metadata

Field	Value
Publication number	US-10679979-B2
Application number	US-201816150913-A
Country	US
Kind code	B2
Filing date	Oct 3, 2018
Priority date	Mar 17, 2000
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of first wirings extending in a first direction, the plurality of first wirings are arranged adjacent to each other in a second direction on a layer level;
a second wiring that is apart from the plurality of first wirings in the second direction on the layer level; and
a plurality of dummy wirings arranged between the plurality of first wirings and the second wiring on the layer level, wherein the plurality of dummy wirings are arranged at a plurality of crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction, wherein:
the third direction and the fourth direction are neither parallel nor orthogonal to the first direction and the second direction,
the plurality of dummy wirings having:
a first dummy wiring;
a second dummy wiring; and
a third dummy wiring, wherein centers of the second dummy wiring and the third dummy wiring are nearest to a center of the first dummy wiring relative to others of the plurality of dummy wirings, and

the respective centers of the first dummy wiring, the second dummy wiring, and the third dummy wiring are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first direction and the second direction,
the plurality of dummy wirings are square-shaped in a plan view,
a distance between the first dummy wiring and the second dummy wiring is smaller than a length of each side of the first dummy wiring, and
a distance between the first dummy wiring and the third dummy wiring is smaller than the length of each side of the first dummy wiring.

2. The semiconductor device according to claim 1 , wherein an angle between the third virtual linear line and the first direction is between 15 and 25° and an angle between a fourth virtual linear line and the second direction is between 15 and 25°.

3. The semiconductor device according to claim 1 , wherein an angle between the third virtual linear line and the first direction is between 2 and 40°, and an angle between a fourth virtual linear line and the second direction is between 2 and 40°.

4. The semiconductor device of according to claim 1 , wherein each distance between adjacent ones of the plurality of dummy wirings is about half of a length of each side of each of the plurality of dummy wirings.

5. The semiconductor device according to claim 1 , wherein a plan area of layers of the dummy wirings occupies a unit plan area at a rate of 30-50%.

6. The semiconductor device according to claim 1 , wherein an angle between the third virtual linear line and the first direction is between 2 and 40° and the dummy wirings are formed from an alloy of aluminum and copper.

7. The semiconductor device according to claim 1 , wherein an angle between the third virtual linear line and the first direction is between 2 and 40°, an angle between the fourth virtual linear line and the second direction is between 2 and 40°, a via plug connects a wiring on another layer level with the plurality of first wirings or the second wiring on the layer level, and the via plug is made of tungsten.

8. The semiconductor device according to claim 7 , wherein the distance between the first dummy wiring and the second dummy wiring is in a range of 0.5 to 5.0 μm.

9. The semiconductor device according to claim 7 , wherein the distance between the first dummy wiring and the second dummy wiring is approximately 1.0 μm and the distance between the first dummy wiring and the third dummy wiring is approximately 1.0 μm.

10. A semiconductor device comprising:
a plurality of first wirings extending in a first direction, the plurality of first wirings are arranged adjacent to each other in a second direction on a layer level;
a second wiring that is apart from the plurality of first wirings in the second direction on the layer level; and
a plurality of dummy wirings arranged between the plurality of first wirings and the second wiring on the layer level, wherein the plurality of dummy wirings are arranged at a plurality of crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction, wherein:
the third direction and the fourth direction are neither parallel nor orthogonal to the first direction and the second direction,
the plurality of dummy wirings having:
a first dummy wiring;
a second dummy wiring; and
a third dummy wiring, wherein centers of the second dummy wiring and the third dummy wiring are nearest to a center of the first dummy wiring relative to others of the plurality of dummy wirings,

wherein the respective centers of the first dummy wiring, the second dummy wiring, and the third dummy wiring are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first direction and the second direction,
wherein the dummy wirings have a polygonal shape and rotational symmetries through 90 degrees about respective centers of the dummy wirings, and
wherein an angle between the third virtual linear line and the first direction is between 2 and40°.

11. The semiconductor device according to claim 10 , wherein the dummy wirings are formed from an alloy of aluminum and copper.

12. The semiconductor device according to claim 10 , further comprising a via plug connecting a wiring on another layer level to the first or second wiring on the layer level, wherein the via plug is made of tungsten.

Assignees

• Seiko Epson Corp

Inventors

• Mori Katsumi
• Kawahara Kei
• Kasuya Yoshikazu

Classifications

• H01L2924/00

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic