Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium

Patent metadata

Field	Value
Publication number	US-9455223-B2
Application number	US-201514613824-A
Country	US
Kind code	B2
Filing date	Feb 4, 2015
Priority date	Mar 17, 2000
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

First claim

What is claimed is:

1. A multilayer semiconductor device comprising:
a plurality of first wirings extending in a first direction,
the first wirings are arranged adjacent to each other in a second direction on a layer level;
a second wiring that is apart from the first wirings in the second direction on the layer level; and
a plurality of dummy wirings arranged between the first wirings and the second wiring on the layer level,
the dummy wirings are arranged at a plurality of crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction, wherein:
the third direction and the fourth direction are neither parallel nor orthogonal to the first direction and the second direction.

2. The multilayer semiconductor device of claim 1 , wherein the second direction and the first virtual linear lines define an angle of 2 to 40 degree.

3. The multilayer semiconductor device of claim 1 , wherein the first virtual linear lines are spaced a first pitch from one another.

4. The multilayer semiconductor device of claim 3 , wherein the second virtual linear lines are spaced a second pitch from one another.

5. The multilayer semiconductor device of claim 1 , wherein the dummy wirings disposed next to one another on each of the first virtual linear lines are mutually offset in the first direction.

6. The multilayer semiconductor device of claim 5 , wherein the dummy wirings disposed next to one another on each of the second virtual linear lines are mutually offset in the second direction.

7. The multilayer semiconductor device of claim 1 , wherein the third direction and the fourth direction are perpendicularly oriented.

8. The multilayer semiconductor device of claim 1 , further comprising:
a prohibited area where is not allowed to create the dummy wirings is arranged around the first wirings.

9. The multilayer semiconductor device of claim 1 , wherein a center of each of the dummy wirings is located on one of the first virtual linear lines.

10. The multilayer semiconductor device of claim 9 , wherein a center of each of the dummy wirings is located on one of the second virtual linear lines.

11. The multilayer semiconductor device of claim 1 , wherein the dummy wirings have a side oriented parallel or perpendicular to the first direction.

12. The multilayer semiconductor device of claim 11 , wherein the dummy wirings have a square shape.

13. A method for manufacturing the multilayer semiconductor device of claim 1 comprising:
making a first insulating layer;
making the first wirings, the second wiring and the dummy wirings on the first insulating layer;
making a second insulating layer on the first wirings, the second wiring and the dummy wirings; and
polishing the second insulating layer.

14. A method for manufacturing the multilayer semiconductor device of claim 13 , wherein the second insulating layer is polished by a chemical mechanical polishing method.

Assignees

• Seiko Epson Corp

Inventors

• Mori Katsumi
• Kawahara Kei
• Kasuya Yoshikazu

Classifications

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title