Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium

Patent metadata

Field	Value
Publication number	US-10121741-B2
Application number	US-201715441635-A
Country	US
Kind code	B2
Filing date	Feb 24, 2017
Priority date	Mar 17, 2000
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.

First claim

What is claimed is:

1. A multilayer semiconductor device comprising:
a plurality of first wirings extending in a first direction, the plurality of first wirings are arranged adjacent to each other in a second direction on a layer level;
a second wiring that is apart from the plurality of first wirings in the second direction on the layer level; and
a plurality of dummy wirings arranged between the plurality of first wirings and the second wiring on the layer level, wherein the plurality of dummy wirings are arranged at a plurality of crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction, wherein:
the third direction and the fourth direction are neither parallel nor orthogonal to the first direction and the second direction,
the plurality of dummy wirings having:
a first dummy wiring;
a second dummy wiring; and
a third dummy wiring, wherein centers of the second dummy wiring and the third dummy wiring are nearest to a center of the first dummy wiring relative to others of the plurality of dummy wirings, and
the respective centers of the first dummy wiring, the second dummy wiring, and the third dummy wiring are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first direction and the second direction.

2. The semiconductor device according to claim 1 ,
the plurality of dummy wirings having:
a fourth dummy wiring;
a fifth dummy wiring, wherein centers of the fourth dummy wiring and the fifth dummy wiring are nearest to a center of the first dummy wiring relative to other of the plurality of dummy wirings;
wherein respective centers of the first dummy wiring, the fourth dummy wiring, and the fifth dummy wiring are aligned on a fourth virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first direction and the second direction.

3. The semiconductor device according to claim 2 , wherein an angle between the third virtual linear line and the first direction is the same as an angle between the fourth virtual linear line and the second direction.

4. The semiconductor device according to claim 3 , wherein the angle between the third virtual linear line and the first direction is between 2 and 40°.

5. The semiconductor device according to claim 3 , wherein the angle between the third virtual linear line and the first direction is between 15 and 25°.

6. The semiconductor device according to claim 2 , wherein an angle between the fourth virtual linear line and the second direction is between 2 and 40°.

7. The semiconductor device according to claim 2 , wherein an angle between the fourth virtual linear line and the second direction is between 15 and 25°.

8. The semiconductor device according to claim 2 , wherein the fourth virtual linear line is perpendicular to the third virtual linear line.

9. The semiconductor device according to claim 1 , wherein an angle between the third virtual linear line and the first direction is between 2 and 40°.

10. The semiconductor device of according to claim 1 , wherein an angle between the third virtual linear line and the first direction is between 15 and 25°.

11. The semiconductor device according to claim 1 , wherein the dummy wirings are square-shaped in a plan view.

12. The semiconductor device according to claim 1 , wherein the dummy wirings have a square shape in a plan view.

13. The semiconductor device according to claim 1 ,
wherein each of the dummy wirings has a first side, a second side parallel to the first side, a third side perpendicular to the first side, and a fourth side parallel to the third side, and
wherein the first side, the second side, the third side, and the fourth side are the same length.

Assignees

• Seiko Epson Corp

Inventors

• Mori Katsumi
• Kawahara Kei
• Kasuya Yoshikazu

Classifications

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title