Method for assembling two substrates of different natures via a ductile intermediate layer

Patent metadata

Field	Value
Publication number	US-10679963-B2
Application number	US-201414893396-A
Country	US
Kind code	B2
Filing date	May 26, 2014
Priority date	May 27, 2013
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A method for manufacturing a heterostructure, including: contacting a first substrate having a first coefficient of thermal expansion and a second substrate having a different second coefficient of thermal expansion; annealing an assembly formed by contacting the first substrate and the second substrate; after annealing, returning the assembly to room temperature; providing, before the contacting, at least one intermediate layer at a surface of at least one of the first and second substrates, the at least one intermediate layer being made of a material which is ductile during the annealing and returning to room temperature; performing the contacting with the at least one intermediate layer sandwiched between the first and the second substrates; upon returning to room temperature, applying an outer pressure to the assembly to maintain it compressed.

First claim

The invention claimed is:

1. A method for manufacturing a heterostructure, the method comprising:
contacting a first substrate and a second substrate with at least one intermediate layer sandwiched between the first and second substrates, thereby forming an assembly;
annealing the assembly at an annealing temperature greater than room temperature; and
after the annealing, applying and maintaining a uniaxial outer pressure to the assembly to compress the assembly while cooling the assembly to room temperature, thereby forming a bonded structure of the first and second substrates;
wherein
the first substrate has a first coefficient of thermal expansion,
the second substrate has a second coefficient of thermal expansion different from the first coefficient of thermal expansion,
the at least one intermediate layer is present at a surface of at least one of the first substrate and the second substrate before the contacting, and
the at least one intermediate layer is a metal layer which is ductile during the annealing and the cooling to room temperature.

2. The method according to claim 1 , wherein the annealing is implemented during a thermal compression aided bonding of the first and second substrates with the at least one intermediate layer sandwiched between the first and second substrates.

3. The method according to claim 1 , wherein
the contacting is a direct bonding of the first and second substrates with the at least one intermediate layer sandwiched between the first and second substrates, and
the annealing is a bonding strengthening annealing.

4. The method according to claim 3 , further comprising
compressing the assembly during at least part of the bonding strengthening annealing.

5. The method according to claim 1 , wherein a radius of curvature of the assembly is maintained greater than 10 meters during the cooling to room temperature.

6. The method according to claim 1 , further comprising:
before the contacting, softening the at least one intermediate layer to reduce a yield strength thereof.

7. The method according to claim 6 , wherein the softening is performed by thermal annealing.

8. The method according to claim 6 , wherein the softening is performed by modifying microstructure of the at least one intermediate layer.

9. The method according to claim 1 , further comprising:
before the contacting, forming, by implanting atomic species, an embrittlement area inside the first substrate, and
after the contacting, thinning the first substrate by separating the first substrate at the embrittlement area.

10. The method according to claim 1 , wherein the first and second substrates are substrates of materials which are in a state of elastic deformation during the annealing and the cooling to room temperature.

11. The method according to claim 1 , wherein the at least one intermediate layer is a layer deposited on the surface of at least one of the first and second substrates.

12. The method according to claim 11 , wherein the first substrate is a silicon substrate, the second substrate is an indium phosphide substrate, and the at least one intermediate layer is a copper layer.

13. The method according to claim 1 , wherein the at least one intermediate layer is a surface layer of the second substrate.

14. The method according to claim 13 , wherein the first substrate is a silicon substrate, and the second substrate is a copper substrate.

15. The method according to claim 1 , wherein a radius of curvature of the assembly is maintained greater than 80 meters during the cooling to room temperature.

16. The method according to claim 1 , wherein a barrier layer is interposed between the at least one intermediate layer and one of the first and second substrates.

17. The method according to claim 1 , wherein the uniaxial outer pressure ranges from 0.1 to 7.64 MPa.

18. The method according to claim 1 , wherein the annealing temperature ranges from 30° C. to 400° C.

19. The method according to claim 1 , wherein the annealing temperature ranges from 200° C. to 400° C.

Assignees

• Commissariat Energie Atomique

Inventors

• Imbert Bruno
• Benaissa Lamine
• Gondcharton Paul

Classifications

• H01L2224/83895

  Electricity · mapped topic

• H01L21/187

  Electricity · mapped topic

• H01L2924/10335

  Electricity · mapped topic

• H01L2224/83203

  Electricity · mapped topic

• H01L2924/3511

  Electricity · mapped topic