Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness

Patent metadata

Field	Value
Publication number	US-10679906-B2
Application number	US-201816036984-A
Country	US
Kind code	B2
Filing date	Jul 17, 2018
Priority date	Jul 17, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness generally include a bilayer spacer adjacent a dummy gate disposed on a nanosheet stack. The bilayer spacer includes an inner spacer layer on sidewalls of the gate and a sacrificial layer on the inner spacer layer. The sacrificial layer can be laterally trimmed to bring the in situ doped source/drain regions closer to the channel, which improves junction sharpness. Additionally, the sacrificial spacer layer can be later removed during the process for forming the transistor so as to form an airgap spacer adjacent the gate, which minimizes parasitic capacitance.

First claim

What is claimed is:

1. A method for forming a nanosheet transistor with reduced parasitic capacitance and improved junction sharpness, the method comprising:
depositing a bilayer comprising an inner spacer layer and a sacrificial layer on a dummy gate, wherein the dummy gate is formed on a nanosheet stack comprising Si layers and SiGe layers;
laterally etching the SiGe layers relative to the Si layers such that W is greater than t, wherein W is a lateral etch width and t is a gap distance between Si layers;
forming an inner spacer adjacent the SiGe layers having a width such that the Si layers have exposed end portions;
epitaxially growing source/drain regions from the exposed end portions of the Si layers;
depositing an interlevel dielectric layer;
selectively removing the dummy gate and remaining portions of the SiGe layers and depositing a high-k dielectric-metal gate structure therein;
forming contacts in the interlevel dielectric layer to the source/drain regions;
selectively removing the sacrificial layer to form a gap between the inner spacer layers adjacent the high-k dielectric-metal gate structure and the contacts; and
non-conformally depositing a dielectric into the gap to form an airgap spacer therein.

2. The method of claim 1 , wherein the inner spacer of the bilayer comprises SiBCN and the sacrificial layer comprises SiCO.

3. The method of claim 1 , wherein laterally etching the SiGe layers from the nanosheet stacks comprises exposing the SiGe layers to HCl vapor.

4. The method of claim 1 , wherein forming the inner spacer adjacent the SiGe layers comprises conformally depositing a dielectric layer at a thickness effective to pinch off between the Si layers followed by etch back with an overetch to provide the exposed end portions of the Si layers.

5. The method of claim 4 , wherein the dielectric layer comprises silicon nitride.

6. The method of claim 1 further comprising laterally trimming the sacrificial layer prior to depositing the interlevel dielectric layer to provide a recess between the inner spacer layer about the high-k dielectric-metal gate structure and an inner sidewall of the source/drain region.

7. The method of claim 6 , wherein forming the contacts in the interlevel dielectric layer to the source/drain regions fills the recess.

8. The method of claim 6 , wherein the SiGe has a germanium content from about 5 atomic percent to about 70 atomic percent.

9. A method for forming a nanosheet transistor with reduced parasitic capacitance and improved junction sharpness, the method comprising:
depositing a dummy gate onto the nanosheet stack and sidewalls thereof, the nanosheet stack comprising epitaxially deposited silicon layers sandwiched between SiGe layers;
depositing a bilayer spacer onto sidewalls of the dummy gate comprising a SiBCN layer in direct contact with the sidewalls and a SiCO sacrificial layer on the SiBCN layer;
recessing the nanosheet stack to form openings for source or drain regions, wherein the openings are self-aligned to the SiCO sacrificial layer;
laterally etching the SiGe layers to create a gap between Si layers, wherein W>t, wherein W is a lateral etch width of the SiGe removed and t is a vertical distance between Si layers;
conformally depositing a first dielectric layer in an amount effective to fill the gap between the Si layers;
etching back the first dielectric layer to form an inner spacer layer of the first dielectric on sidewalls of the SiGe layers and expose end portions of the Si layers;
epitaxially growing the source/drain regions from the exposed end portions of the Si layers to the substrate;
removing the dummy gate and the SiGe layer between the Si layers to form openings therein;
forming a high-k dielectric-metal gate structure in the openings;
recessing a top portion of the high-k dielectric-metal gate structure and depositing a dielectric gate cap therein;
forming contacts to the source or drain regions;
selectively removing the SiCO sacrificial spacer layer to form a gap between the high-k dielectric-metal gate structure and the contacts; and
non-conformally depositing a second dielectric in the gap for form an airgap spacer.

10. The method of claim 9 further comprising planarizing the structure to the gate cap.

11. The method of claim 9 , wherein the dielectric layer comprises silicon nitride.

12. The method of claim 9 , wherein the substrate includes a buried oxide layer.

13. The method of claim 9 , wherein selectively removing the SiGe layers from the nanosheet stacks comprises exposing the SiGe layers to HCl vapor.

14. The method of claim 9 further comprising laterally trimming the SiCO sacrificial layer subsequent to epitaxially growing the source/drain regions to form a recess between the inner SiBCN spacer and an inner sidewall of the source/drain regions.

15. The method of claim 14 , wherein forming contacts to the source or drain regions fills the recess.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Park Chanro
• Xie Ruilong
• Yamashita Tenko

Classifications

• H01L21/823814

  Electricity · mapped topic

• H01L29/78651

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/02532

  Electricity · mapped topic