Method of forming inner spacers on a nano-sheet/wire device

Patent metadata

Field	Value
Publication number	US-9799748-B1
Application number	US-201715398335-A
Country	US
Kind code	B1
Filing date	Jan 4, 2017
Priority date	Jan 4, 2017
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A method includes forming a stack of semiconductor material layers above a substrate. The stack includes at least one first semiconductor material layer and at least one second semiconductor material layer. A first etching process is performed on the stack to define cavities. The cavities expose end portions of the first and second semiconductor material layers. Portions of the first semiconductor material layer are removed to define end recesses. A layer of insulating material is formed in the end recesses and at least partially fills the cavities. A second etching process is performed on the stack to remove end portions of the at least one second semiconductor material layer and to remove portions of the layer of insulating material in the cavities not disposed between the first and second semiconductor material layers so as to form inner spacers on ends of the at least one first semiconductor material layer.

First claim

What is claimed:

1. A method, comprising:
forming a stack of semiconductor material layers above a substrate, said stack including at least one first semiconductor material layer and at least one second semiconductor material layer, wherein said first and second semiconductor material layers are arranged in alternating fashion and wherein said first and second semiconductor material layers are comprised of materials that may be selectively etched relative to one another;
performing a first etching process on said stack to define cavities in said stack, said cavities exposing end portions of said first and second semiconductor material layers;
removing portions of said at least one first semiconductor material layer to define end recesses;
forming a layer of insulating material in said end recesses and at least partially filling said cavities; and
performing a second etching process on said stack to remove end portions of said at least one second semiconductor material layer and to remove portions of said layer of insulating material in said cavities not disposed between said first and second semiconductor material layers so as to form inner spacers on ends of said at least one first semiconductor material layer.

2. The method of claim 1 , further comprising:
forming a gate structure above said stack;
forming a spacer structure on sidewalls of said gate structure;
performing said first etching process in the presence of said spacer structure;
removing at least a portion of said spacer structure; and
performing said second etching process after removing said at least said portion of said spacer structure.

3. The method of claim 2 , wherein said spacer structure comprises a first spacer and a second spacer formed above said first spacer, and removing said at least said portion of said spacer structure comprises removing said second spacer.

4. The method of claim 2 , further comprising:
removing said gate structure to define a gate cavity exposing said stack of semiconductor material layers;
removing a portion of said at least one first semiconductor material layer exposed by said gate cavity; and
forming a replacement gate structure in said gate cavity and in a space created by the removal of said portion of said at least one first semiconductor material layer.

5. The method of claim 2 , wherein performing said second etch process comprises etching said layer of insulating material to define a second spacer on said spacer structure.

6. The method of claim 1 , wherein forming said layer of insulating material comprises performing a conformal deposition process.

7. The method of claim 1 , further comprising forming a source/drain material in said cavities, wherein said inner spacers are disposed between said at least one first semiconductor material layer and said source/drain material.

8. The method of claim 1 , wherein said at least one first semiconductor material layer comprises silicon germanium, and said at least one second semiconductor material layer comprises silicon.

9. The method of claim 1 , wherein said at least one first semiconductor material layer comprises a plurality of first semiconductor material layers, and said at least one second semiconductor material layer comprises a plurality of second semiconductor material layers alternating with said plurality of said first semiconductor material layers.

10. The method of claim 1 , wherein said end portions of said at least one second semiconductor material layer comprises rounded end portions.

11. A method, comprising:
forming a stack of semiconductor material layers above a substrate, said stack including at least one first semiconductor material layer and at least one second semiconductor material layer, wherein said first and second semiconductor material layers are arranged in alternating fashion and wherein said first and second semiconductor material layers are comprised of materials that may be selectively etched relative to one another;
forming a gate structure above said stack;
forming a spacer structure on sidewalls of said gate structure;
etching said stack using said gate structure and said spacer structure as an etch mask to define cavities in said stack, said cavities exposing end portions of said first and second semiconductor material layers;
removing a portion of said spacer structure to define a reduced width spacer structure;
removing portions of said at least one first semiconductor material layer to define end recesses;
forming a layer of insulating material in said end recesses and at least partially filling said cavities; and
etching said stack using said gate structure and said reduced width spacer structure as an etch mask to remove end portions of said at least one second semiconductor material layer and to remove portions of said layer of insulating material not disposed between said first and second semiconductor material layers so as to form inner spacers on ends of said at least one first semiconductor material layer.

12. The method of claim 11 , wherein said spacer structure comprises a first spacer and a second spacer formed above said first spacer, and removing said portion of said spacer structure comprises removing said second spacer.

13. The method of claim 11 , wherein forming said layer of insulating material comprises performing a conformal deposition process.

14. The method of claim 13 , wherein etching said stack using said gate structure and said reduced width spacer structure as an etch mask comprises etching said layer of insulating material to define a second spacer on said spacer structure.

15. The method of claim 11 , further comprising forming a source/drain material in said cavities, wherein said inner spacers are disposed between said at least one first semiconductor material layer and said source/drain material.

16. The method of claim 11 , further comprising:
removing said gate structure to define a gate cavity exposing said stack of semiconductor material layers;
removing a portion of said at least one first semiconductor material layer exposed by said gate cavity; and
forming a replacement gate structure in said gate cavity and in a space created by the removal of said portion of said at least one first semiconductor material layer.

17. The method of claim 11 , wherein said at least one first semiconductor material layer comprises silicon germanium, and said at least one second semiconductor material layer comprises silicon.

18. The method of claim 11 , wherein said at least one first semiconductor material layer comprises a plurality of first semiconductor material layers, and said at least one second semiconductor material layer comprises a plurality of second semiconductor material layers alternating with said plurality of said first semiconductor material layers.

19. The method of claim 11 , wherein said end portions of said at least one second semiconductor material layer comprises rounded end portions.

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Sung Min Gyu
• Park Chanro
• Kim Hoon

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/694 Primary

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H01L21/3085

  Electricity · mapped topic

• H01L29/66553 Primary

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic