Shared bit line array architecture for magnetoresistive memory

Patent metadata

Field	Value
Publication number	US-10679685-B2
Application number	US-201715855660-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Dec 27, 2017
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A magnetoresistive memory architecture in one aspect includes a plurality of bit lines each coupled to two or more respective columns of magnetoresistive memory cells, and a plurality of source lines each coupled to a respective one of the columns of memory cells. A given memory cell can be accessed by biasing a selected word line, a selected bit line, and a selected source line coupled to corresponding column of memory cells coupled to the selected bit line, and by counter biasing one or more selected source lines coupled to one or more other columns of memory cells coupled to the selected bit line.

First claim

What is claimed is:

1. A memory device comprising:
a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell includes a Magnetic Tunneling Junction (MTJ) and a transistor, wherein a drain of the transistor is coupled to a first terminal of the MJT;
a plurality of bit lines, wherein each bit line is coupled to a second terminal of the MTJs of the memory cells in two or more respective columns of the memory cells;
a plurality of source lines, wherein each source line is coupled to a source of the transistors of the memory cells in a respective column of the memory cells;
a plurality of word lines, wherein each word line is coupled to a gate of the transistors of the memory cells in a respective row of the memory cells; and
a control circuit configured to apply corresponding biases to a select word line, the plurality of bit lines and the plurality source lines to write data in parallel to cells in the select word line, including biases to a select bit line and a select source line coupled to the select hit line, and to apply a corresponding counter bias to one or more other source lines coupled to the select bit line to write a given value to a given memory cell.

2. The memory device of claim 1 , wherein the control circuit is further configured to:
apply a word line write voltage to the select word line;
apply a bit line write voltage to the select hit line;
apply a ground voltage to the select source line;
apply the bit line write voltage to the one or more other source lines coupled to the select bit line; and
wherein a ‘0’ state is written to the given memory cell.

3. The memory device of claim 2 , wherein the control circuit is further configured to:
apply a word line write voltage to the select word line;
apply a ground voltage to the select bit hue;
apply a source line write voltage to the select source line;
apply the ground voltage to the one or more other source lines coupled to the select bit line; and
wherein a ‘1’ state is written to the given memory cell.

4. The memory device of claim 1 , wherein the control circuit is further configured to apply corresponding biases to the select word line, the select bit line and the select source line coupled to the select bit line, and to apply a corresponding counter bias to one or more other source lines coupled to the select bit line to read the given memory cell from the select bit line.

5. The memory device of claim 4 , wherein the control circuit is further configured to:
apply a word line read voltage to the select word line;
apply a bit line read voltage to the select bit line;
apply a ground voltage to the select source line; and
apply the bit line read voltage to the one or more other source lines coupled to the select bit line.

6. The memory device of claim 1 , wherein the control circuit is further configured to:
apply a word line read voltage to the select word line;
apply aground voltage to the select bit line;
apply a source line read voltage to the select source line;
apply the ground voltage to the one or more other source lines coupled to the select bit line; and
wherein the given memory cell is read from the select bit line.

7. The memory device according to claim 1 , wherein the plurality of memory cells comprise, a plurality of spin torque magnetoresistive memory cells.

8. The memory device according, to claim 1 , wherein
the plurality of bit lines and the plurality of source lines are substantially parallel to each other; and
the plurality of word lines are substantially parallel to each other and substantially perpendicular to the plurality of bit lines and the plurality of source lines.

9. A Magnetoresistive Random-Access Memory (MRAM) comprising:
a memory cell array including;
a plurality of magnetoresistive memory cells arranged in a plurality of columns and rows;
a plurality of word lines, wherein each word line is coupled to a corresponding row of the magnetoresistive memory cells;
a plurality of bit lines, wherein each bit line is coupled to a first one and a second one of a pair of columns of the magnetoresistive memory cells; and
a plurality of pairs of source lines, wherein a first one of each pair of source lines is coupled to corresponding first ones of the pair of columns of the magnetoresistive memory cells and a second one of each pair source lines is coupled to corresponding second ones of the pair of columns of the magnetoresistive memory cells; and

a control circuit coupled to memory cell array, wherein the control circuit is configured bias a select word line, bias the plurality of bit lines, bias the first ones of the pairs of source lines and counter bias the second one of the pairs of source line relative to the first one of the pairs of source lines to access magnetoresistive memory cell in the select word line.

10. The MRAM of claim 9 , wherein the control circuit is further configured to:
bias the select word line at a word line write voltage;
bias a given one of the bit lines at a bit line write voltage;
bias a corresponding one of the first source lines at a ground voltage; and
bias a corresponding one of the second source lines at the bit line write voltage, wherein a ‘0’ state is written to a given memory cell.

11. The MRAM of claim 10 , wherein the control circuit is further configured to:
bias the select word line at a word line write voltage;
bias a given one of the bit line at a ground voltage;
bias a corresponding one of the first source lines at a source line write voltage; and
bias a corresponding one of the second source lines at the ground voltage, wherein a ‘1’ state is written to the given memory cell.

12. The MRAM of claim 9 , wherein the control circuit is further configured to:
bias the select word line at a word line read voltage;
bias a given one of the bit line a bit line read voltage;
bias a corresponding one of the first source lines at a ground voltage; and
bias a corresponding one of the second source lines at the bit line read voltage, wherein a state of a given memory cell is read from the corresponding one of first source line.

13. The MRAM of claim 9 , wherein the control circuit is further configured to:
bias the select word line at a word line read voltage;
bias a given one of the bit line a ground voltage;
bias a corresponding one of the first source lines at a source line read voltage; and
bias a corresponding one of the second source lines at the ground voltage, wherein at state of the given memory cell is read from the bit line.

14. The MRAM according to claim 9 , wherein the plurality of magnetoresistive memory cells comprise, a plurality of spin torque magnetoresistive memory cells.

15. The MRAM according to claim 14 , wherein the plurality of spin torque magnetoresistive memory cells each comprise, a pillar including:
one or more seed layers;
one or more synthetic antiferromagnetic layers;
one or more reference magnetic layers;
one or more magnetic tunneling barrier layers;
one or more free magnetic layers;
one or more non-magnetic spacer layers;
one or more perpendicular polarizer layers;
one or more capping layers; and
one or more hard mask layers.

16. A method of accessing a Magnetoresistive Random-Access Memory (MRAM) comprising:
biasing a selected word line coupled to a row of a plurality of Magnetic Tunnel Junction (MTJ) memory cells including a given MTJ memory cell;
biasing a plurality of bit lines in parallel, including biasing a selected bit line coupled to a first and a second column of the plurality of

Assignees

• Spin Memory Inc

Inventors

• Hoang Loc
• Levi Amitay

Classifications

• H01L27/228

  Electricity · mapped topic

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2213/82

  Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title