Method for manufacturing MTJ memory device

US9406876B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9406876-B2
Application numberUS-201615041325-A
CountryUS
Kind codeB2
Filing dateFeb 11, 2016
Priority dateJul 25, 2014
Publication dateAug 2, 2016
Grant dateAug 2, 2016

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Abstract

Official abstract text for this publication.

A method for manufacturing MTJ pillars for a MTJ memory device. The method includes depositing multiple MTJ layers on a substrate, depositing a hard mask on the substrate and coating a photoresist on the hard mask. Further, alternating steps of reactive ion etching and ion beam etching are performed to isolate MTJ pillars and expose side surfaces of the MTJ layers. An insulating layer is the applied to protect the side surfaces of the MTJ layers. A second insulating layer is deposited before the device is planarized using chemical mechanical polishing.

First claim

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What is claimed is: 1. A method of manufacturing a magnetic tunnel junction (“MTJ”) device, the method comprising: depositing a plurality of MTJ layers on a substrate wafer, the plurality of MTJ layers including a reference layer, a barrier layer disposed on the reference layer and a free layer disposed on the barrier layer; depositing a hard mask above the plurality of MTJ layers; forming a first photoresist layer on a portion of the hard mask; etching the hard mask and the plurality of MTJ layers to form an MTJ pillar under the first photoresist layer, wherein the free layer and barrier layer are etched to expose side surfaces of the free layer and the barrier layer of the MTJ structure; depositing a first insulating layer on the MTJ pillar, on the exposed side surfaces of the free layer and the barrier layer, and on an exposed surface of the reference layer; etching the MTJ pillar to remove portions of the first insulating layer disposed on horizontal surfaces of the MTJ pillar but leaves portions of the first insulating layer on the exposed side surfaces of the free layer and barrier layer, and to electrically isolate the MTJ pillar from adjacent MTJ pillars; and planarizing the substrate wafer, wherein the step of etching the hard mask and the plurality of MTJ layers includes at least one reactive ion etching and at least one ion beam etching, wherein the at least one ion beam etching ends with an ion beam etch at a high ion beam angle. 2. The method of manufacturing according to claim 1 wherein the high ion beam angle is seventy degrees. 3. The method of manufacturing according to claim 1 , wherein the step of etching the MTJ pillar to remove portions of the first insulating layer is performed using ion beam etching. 4. The method of manufacturing according to claim 1 , wherein the step of depositing a plurality of MTJ layers further comprises: depositing a tantalum nitride capping layer on the free layer; and depositing a perpendicular polarizer on the tantalum nitride capping layer. 5. The method of manufacturing according to claim 4 , wherein the step of etching the hard mask and the plurality of MTJ layers further comprises: reactive ion etching the hard mask; ion beam etching the perpendicular polarizer; reactive ion etching the tantalum nitride capping layer; ion beam etching the free layer and the barrier layer, wherein the ion beam etching the free layer and the barrier layer step ends with an ion beam etch at a high ion beam angle. 6. The method of manufacturing according to claim 5 , wherein the free layer comprises a CoFeB thin film, which serves as an etch stop for the reactive ion etching of the tantalum nitride capping layer. 7. The method of manufacturing according to claim 5 , wherein after the step of ion beam etching the perpendicular polarizer, a third insulating layer is conformally deposited on the MTJ pillar. 8. The method of manufacturing according to claim 7 , further comprising etching the MTJ pillar to remove a portion of the third insulating layer that is disposed on horizontal surfaces of the MTJ structure. 9. The method of manufacturing according to claim 1 , wherein the step of etching the MTJ pillar to remove a portion of the first insulating layer comprises applying ion beams at a normal angle relative to the substrate wafer. 10. The method of manufacturing according to claim 1 , further comprising conformally depositing a second insulating layer on the MTJ pillar after the step of ion beam etching the MTJ pillar. 11. The method of manufacturing according to claim 1 , wherein the barrier layer comprises an oxide of magnesium. 12. The method of manufacturing according to claim 5 , further comprising stopping the ion beam etching of the barrier layer using secondary ion mass spectroscopy end point detection. 13. The method of manufacturing according to claim 1 , further comprising forming a second photoresist layer on the first insulating layer on the MTJ pillar before the step of etching the MTJ pillar to remove a portion of the first insulating layer. 14. The method of manufacturing according to claim 13 , wherein the second photoresist layer has a width over the MTJ pillar that is larger than a width of the first photoresist layer. 15. A method of manufacturing a magnetic tunnel junction (“MTJ”) device, the method comprising: depositing a plurality of MTJ layers on a substrate wafer, the plurality of MTJ layers including a reference layer, a barrier layer disposed on the reference layer and a free layer disposed on the barrier layer; depositing a hard mask above the plurality of MTJ layers; forming a first photoresist layer on a portion of the hard mask; reactive ion etching the hard mask; ion beam etching the free layer and the barrier layer to expose side surfaces of the free layer and barrier layer, thereby forming an MTJ pillar, wherein the ion beam etching the free layer and the barrier layer step ends with an ion beam etch at a high ion beam angle; depositing a first insulating layer on the MTJ pillar, on the exposed side surfaces of the free layer and the barrier layer, and on an exposed surface of the reference layer; etching to electrically isolate at least one MTJ pillar to leave portions of the first insulating layer on the exposed side surfaces of the free layer and barrier layer; and planarizing the substrate wafer. 16. The method of manufacturing according to claim 15 wherein the high ion beam angle is seventy degrees. 17. The method of manufacturing according to claim 15 wherein the etching at an angle normal relative to the substrate wafer to isolate at least one MTJ pillar step is performed using ion beam etching. 18. The method of manufacturing according to claim 15 , further comprising conformally depositing a third insulating layer after the step of ion beam etching the at least one upper layer. 19. The method of manufacturing according to claim 18 , further comprising a further step of reactive ion etching to remove horizontal surfaces of the third insulating layer. 20. The method of manufacturing according to claim 19 , further comprising coating a second photoresist layer on the first insulating layer on the MTJ pillar before the step of etching at an angle normal relative to the substrate wafer to isolate at least one MTJ pillar. 21. The method of manufacturing according to claim 20 , wherein the second photoresist layer has a width over the MTJ pillar that is larger than a width of the first photoresist layer.

Assignees

Inventors

Classifications

  • H01L43/12Primary

    Electricity · mapped topic

  • Electricity · mapped topic

  • Materials of the active region · CPC title

  • H10N50/01Primary

    Manufacture or treatment · CPC title

  • H10N50/10Primary

    Magnetoresistive devices · CPC title

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What does patent US9406876B2 cover?
A method for manufacturing MTJ pillars for a MTJ memory device. The method includes depositing multiple MTJ layers on a substrate, depositing a hard mask on the substrate and coating a photoresist on the hard mask. Further, alternating steps of reactive ion etching and ion beam etching are performed to isolate MTJ pillars and expose side surfaces of the MTJ layers. An insulating layer is the ap…
Who is the assignee on this patent?
Spin Transfer Tech Inc
What technology area does this patent fall under?
Primary CPC classification H01L43/12. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).