Register renaming in block-based instruction set architecture

Patent metadata

Field	Value
Publication number	US-2016259645-A1
Application number	US-201514639085-A
Country	US
Kind code	A1
Filing date	Mar 4, 2015
Priority date	Mar 4, 2015
Publication date	Sep 8, 2016
Grant date	—

Abstract

An apparatus for mapping an architectural register to a physical register can include a memory and control circuitry. The memory can be configured to store an intra-core register rename map and an inter-core register rename map. The intra-core register rename map can be configured to map the architectural register to the physical register of a core of a multi-core processor. The inter-core register rename map can be configured to relate the architectural register to an identification of the first core in response to determining that the physical register is a location of a most recent write to the architectural register that has been executed by the first core, is executing on the first core, or is expected to execute on the first core, the most recent write according to program order. The control circuitry can be configured to maintain the intra-core register rename map and the inter-core register rename map.

First claim

What is claimed is:

1 . An apparatus for mapping an architectural register to a physical register, the apparatus comprising:
a memory configured to store an intra-core register rename map and an inter-core register rename map, the intra-core register rename map configured to map the architectural register to the physical register of a first core of a multi-core processor, the inter-core register rename map configured to relate the architectural register to an identification of the first core in response to determining that the physical register is a location of a most recent write to the architectural register that has been executed by the first core, is executing on the first core, or is expected to execute on the first core, the most recent write being according to a program order; and control circuitry configured to maintain the intra-core register rename map and the inter-core register rename map.

2 . The apparatus of claim 1 , wherein the multi-core processor is configured according to a block-based microarchitecture, the first core is configured to execute instructions assigned to blocks of instructions, and the blocks of instructions are configured according to a block-based instruction set architecture.

3 . The apparatus of claim 2 , wherein the intra-core register rename map comprises a first input intra-core register rename map associated with a first block of instructions, a first output intra-core register rename map associated with the first block of instructions, a second input intra-core register rename map associated with a second block of instructions, and a second output intra-core register rename map associated with the second block of instructions.

4 . The apparatus of claim 3 , wherein the apparatus is configured to reference, in conjunction with executing a read instruction, the first input intra-core register rename map to determine if the physical register is the location of the most recent write to the architectural register that has been executed by the first core.

5 . The apparatus of claim 3 , wherein the first output intra-core register rename map is the second input intra-core register rename map.

6 . The apparatus of claim 5 , wherein the intra-core register rename map comprises a record that corresponds to the architectural register, the record having a first field to store an identification of the physical register that has been mapped to the architectural register, the record having a second field, a value of the second field configured to indicate if the physical register is the location of the most recent write to the architectural register that has been executed by the first core.

7 . The apparatus of claim 6 , wherein the apparatus is configured to determine, in conjunction with executing a write instruction, an intermediate block of instructions between the first block of instructions and a subsequent block of instructions having a subsequent write instruction, and the apparatus is configured to copy the identification of the physical register, stored in the first field of the first output intra-core register rename map, to a corresponding first field of an output intra-core register rename map associated with the intermediate block of instructions.

8 . The apparatus of claim 6 , wherein the first block of instructions includes a block header having a write mask, the write mask having a bit that corresponds to the architectural register, a value of the bit configured to indicate if the architectural register is an object of a write instruction, of the first block of instructions, that is expected to execute on the first core.

9 . The apparatus of claim 8 , wherein the memory is further configured to store a real-time write mask, the control circuitry is further configured to maintain the real-time write mask, the real-time write mask is associated with the first block of instructions, the real-time write mask has a bit that corresponds to the architectural register, and a value of the bit of the real-time write mask is configured to indicate if the architectural register, that is the object of the write instruction, of the first block of instructions, that is expected to execute on the first core, in actuality is to maintain a value that was written by a write instruction of a previous block of instructions.

10 . The apparatus of claim 9 , wherein the apparatus is configured to determine, in response to a determination that the architectural register in actuality is to maintain the value that was written by the write instruction of the previous block of instructions, an intermediate block of instructions between the first block of instructions and a subsequent block of instructions having a subsequent write instruction, and the apparatus is configured to copy the identification of the physical register, stored in the first field of the first input intra-core register rename map, to a corresponding first field of the first output intra-core register rename map and to a corresponding first field of an output intra-core register rename map associated with the intermediate block of instructions.

11 . The apparatus of claim 9 , wherein the apparatus is configured to reference, in conjunction with executing a read instruction, the real-time write mask to determine if the architectural register is the object of the write instruction, of the first block of instructions, that has been executed by the first core, is executing on the first core, or is expected to execute on the first core.

12 . The apparatus of claim 6 , wherein a number of the plurality of intra-core register rename maps is equal to a sum of one added to a number of the blocks of instructions that the first core is configured to execute concurrently, the number of the blocks of instructions that the first core is configured to execute concurrently is equal to a number of arrays of reservation stations of the first core, execution of one block of instructions conveyed to one array of reservation stations is a phase of execution for the one array of reservation stations, and the second output intra-core register rename map is an input intra-core register rename map for an initial block of instructions to be executed on the first core during a subsequent phase of execution.

13 . The apparatus of claim 12 , wherein a second core of the multi-core processor is configured to operate in conjunction with the first core, and the inter-core register rename map comprises a first inter-core register rename map associated with the first core and a second inter-core register rename map associated with the second core.

14 . The apparatus of claim 13 , wherein the first inter-core register rename map comprises a first first inter-core register rename map for the phase of execution and a second first inter-core register rename map for the subsequent phase of execution, and the second inter-core register rename map comprises a first second inter-core register rename map for the phase of execution and a second second inter-core register rename map for the subsequent phase of execution.

15 . The apparatus of claim 14 , wherein the apparatus is configured to reference, in conjunction with executing a read instruction, the first first inter-core register rename map to determine if the first core includes the physical register that is the location of the most recent write to the architectural register that has been executed by the first core, is executing on the first core, or is expected to execute on the first core.

16 . The apparatus of claim 14 , wherein the memory is further configured to store an inter-core wri

Assignees

• Qualcomm Inc

Inventors

• Wright Gregory Michael

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/384 Primary

  Register renaming · CPC title

• G06F9/3858

  Result writeback, i.e. updating the architectural state or memory · CPC title

• G06F9/3854

  Instruction completion, e.g. retiring, committing or graduating · CPC title

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title