Denormalization in multi-precision floating-point arithmetic circuitry

Patent metadata

Field	Value
Publication number	US-10678510-B2
Application number	US-201716333970-A
Country	US
Kind code	B2
Filing date	Sep 25, 2017
Priority date	Oct 27, 2016
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the floating-point arithmetic circuitry may be implemented in specialized processing blocks.

First claim

What is claimed is:

1. An integrated circuit that performs an arithmetic operation of first and second floating-point numbers, comprising:
a partial product generator that generates a partial product of the first and second floating-point numbers;
a rounding circuit coupled to the partial product generator that generates a normalized, rounded product with a first exponent range based on the partial product;
a normalization circuit coupled to the partial product generator that generates a normalized, unrounded product with a second exponent range that is greater than the first exponent range based on the partial product and the first and second floating-point numbers; and
a multiplexer coupled to the rounding circuit and the normalization circuit that selects a product of first and second floating-point numbers among the normalized, unrounded product and the normalized, rounded product based on a control signal.

2. The integrated circuit of claim 1 , wherein the normalization circuit further comprises:
a left shift circuit that receives a processed partial product and shifts the processed partial product to the left based on an additional control signal.

3. The integrated circuit of claim 2 , further comprising:
a control circuit that receives the first and second floating-point numbers and generates the control signal and the additional control signal.

4. The integrated circuit of claim 3 , wherein the first and second floating-point numbers have respective first and second exponents, and wherein the control circuit further comprises:
logic circuitry that receives the first and second exponents and generates the additional control signal by determining if at least one of the first and second floating-point numbers is a denormalized floating-point number based on the first and second exponents.

5. The integrated circuit of any one of claim 3 or 4 , wherein the first and second floating-point numbers have respective first and second mantissas, and wherein the control circuit further comprises:
a first count-leading-zeros circuit that determines first leading zeros of the first mantissa;
a second count-leading-zeros circuit that determines second leading zeros of the second mantissa; and
an adder circuit that adds the first and second leading zeros.

6. The integrated circuit of claim 1 , further comprising:
adder circuitry that receives the product from the multiplexer and a third floating-point number and generates a normalized sum and a rounded sum based on the product and the third floating-point number, and comprises:
an additional multiplexer that outputs a sum of the product and the third floating-point number by selecting between the normalized sum and the rounded sum based on an additional control signal.

7. The integrated circuit of claim 6 , wherein the product and the third floating-point number have respective first and second mantissas and wherein the adder circuitry further comprises:
a fixed-point adder circuit that generates a sum of the first and second mantissas.

8. The integrated circuit of claim 7 , wherein the adder circuitry further comprises:
an additional fixed-point adder circuit coupled to the fixed-point adder circuit that adds a round bit to the sum of the first and second mantissas.

9. The integrated circuit of any one of claim 7 or 8 , wherein the adder circuitry further comprises:
a left shift circuit that generates the normalized sum by shifting the sum of the first and second mantissas a predetermined number of bits to the left.

10. The integrated circuit of claim 6 , wherein the sum of the product and the third floating-point number have a first floating-point precision, further comprising:
a cast function circuit that receives the sum of the product and the third floating-point number from the adder circuitry and generates an upconverted sum by converting the sum from the first floating-point precision into a second floating-point precision that is higher than the first floating-point precision.

11. The integrated circuit of claim 10 , wherein the cast function circuit increases the exponent size of the sum from the first to the second floating-point precision.

12. The integrated circuit of claim 10 , wherein the cast function circuit adjusts the bias of the exponent of the sum from the bias of the first floating-point precision to the bias of the second floating-point precision.

13. A method for performing an arithmetic operation of first and second floating-point numbers with an integrated circuit, comprising:
generating a partial product of the first and second floating-point numbers with a partial product generator;
using a rounding circuit to generate a first product that is normalized and rounded and has a first exponent range based on the partial product;
using a normalization circuit to generate a second product that is normalized and unrounded and has a second exponent range that is greater than the first exponent range based on the partial product and the first and second floating-point numbers; and
generating a product of first and second floating-point numbers by selecting between the first and second products based on a control signal.

14. The method of claim 13 , further comprising:
generating the control signal by determining whether at least one of the first and second floating-point numbers is a denormalized floating-point number.

15. The method of any one of claim 13 or 14 , wherein using the normalization circuit to generate the second product further comprises:
left shifting a processed partial product based on an additional control signal.

16. The method of claim 15 , wherein the first and second floating-point numbers have respective first and second mantissas, further comprising:
determining first leading zeros of the first mantissa;
determining second leading zeros of the second mantissa;
generating a sum signal by adding the first and second leading zeros; and
generating the additional control signal by subtracting one from the sum signal.

17. The method of any one of claims 13 - 14 , wherein the product and a third floating-point number have respective first and second mantissas, further comprising:
using a fixed-point adder circuit to generate a sum of the first and second mantissas;
using an additional fixed-point adder circuit coupled to the fixed-point adder circuit to generate a rounded sum by adding a round bit to the sum of the first and second mantissas; and
using a left shift circuit to generate a normalized sum by shifting the sum of the first and second mantissas a predetermined number of bits to the left.

18. The method of claim 17 , further comprising:
using a multiplexer to select between the rounded sum and the normalized sum.

19. A non-transitory machine readable storage medium encoded with instructions for configuring an integrated circuit that comprises a partial product generator, a normalization circuit coupled to the partial product generator, a rounding circuit coupled to the partial product generator, and a multiplexer coupled to the normalization circuit and the rounding circuit to perform an arithmetic operation of a first floating-point number having a first mantissa and a first exponent that has a first exponent range and a second floating-point number having a second mantissa and a second exponent that has the first exponent range, the instructions comprising:
instructions to configure the partial product generator to generate a partial product of the first and second floating-point numbers;
instr

Assignees

• Altera Corp

Inventors

• Langhammer Martin

Classifications

• G06F7/4876

  Multiplying · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/57 Primary

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F7/49915

  Mantissa overflow or underflow in handling floating-point numbers · CPC title