Ceramic circuit board and semiconductor device using the same

US10674603B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10674603-B2
Application numberUS-201716082526-A
CountryUS
Kind codeB2
Filing dateMar 14, 2017
Priority dateMar 29, 2016
Publication dateJun 2, 2020
Grant dateJun 2, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention provides a ceramic circuit board comprising: a ceramic substrate; and at least one of a recess and a through-hole formed in the ceramic substrate, wherein a conductive portion filled with a conductor is provided in the recess or the through-hole, the surface roughness Ra is 1.0 μm or less, and the maximum height Rz is 100 μm or less. It is preferable that the maximum height Rz is 10 μm or less. Further, it is preferable that the surface roughness Ra is 0.5 μm or less. According to the above-described configuration, it is possible to provide a ceramic circuit board having an excellent positionability of the conductive portion for mounting a semiconductor element.

First claim

Opening claim text (preview).

The invention claimed is: 1. A ceramic circuit board comprising: a ceramic substrate containing any one of aluminum nitride, silicon nitride, aluminum oxide, silicon carbide, silicon oxide, or zirconium oxide; and at least one of a recess or a through-hole formed in the ceramic substrate, the ceramic circuit board comprising a conductive portion which is formed by filling a conductor into the recess or the through-hole, wherein a surface roughness Ra of the ceramic circuit board is 1.0 μm or less; and a maximum roughness height Rz of the ceramic circuit board is 30 μm or less, the surface roughness Ra being measured continuously along an edge of the recess or the through-hole and an edge of the conductive portion, a difference in height between an edge portion of the recess or the through-hole formed to the ceramic substrate and an edge portion of the conductive portion is 0 μm or more and 5 μm or less, the conductor filled in the recess or the through-hole has a filling factor of 98% or more and 100% or less, the conductive portion contains at least one element selected from Cu, Al, Ag or Au as a component, a shortest distance of between adjacent conductive portions, between adjacent recesses, or between adjacent through-holes is 2 mm or less, the maximum roughness height Rz is 10 μm or less, the surface roughness Ra is 0.5 μm or less, and the shortest distance is 0.5 mm or more. 2. The ceramic circuit board according to claim 1 , wherein a diameter of the recess or the through-hole is 1 mm or less. 3. A semiconductor device configured by mounting a semiconductor element on the conductive portion of the ceramic circuit board according to claim 1 . 4. The semiconductor device according to claim 3 , wherein the semiconductor element is mounted so as to stride over the conductive portions. 5. The semiconductor device according to claim 3 , wherein the semiconductor device is a light emitting diode (LED). 6. The semiconductor device according to claim 3 , wherein the shortest distance is 1 mm or less, and the semiconductor device is a light emitting diode (LED). 7. The semiconductor device according to claim 1 , wherein the shortest distance is 1 mm or less.

Assignees

Inventors

Classifications

  • by special treatment of the substrate · CPC title

  • Electricity · mapped topic

  • Treatments characterised by their effect, e.g. heating, cooling, roughening · CPC title

  • wherein the coefficient of thermal expansion is important · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US10674603B2 cover?
The present invention provides a ceramic circuit board comprising: a ceramic substrate; and at least one of a recess and a through-hole formed in the ceramic substrate, wherein a conductive portion filled with a conductor is provided in the recess or the through-hole, the surface roughness Ra is 1.0 μm or less, and the maximum height Rz is 100 μm or less. It is preferable that the maximum heigh…
Who is the assignee on this patent?
Toshiba Kk, Toshiba Materials Co Ltd
What technology area does this patent fall under?
Primary CPC classification H05K1/0306. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 02 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).