Mounting component and electronic device

Patent metadata

Field	Value
Publication number	US-10672722-B2
Application number	US-201916299358-A
Country	US
Kind code	B2
Filing date	Mar 12, 2019
Priority date	Sep 25, 2015
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.

First claim

What is claimed is:

1. A mounting component comprising:
a multilayer structure having a plurality of conducting layers and a plurality of insulating layers alternately stacked on a base material, the plurality of conducting layers being connected by a plurality of interlayer connectors respectively,
the plurality of conducting layers having a first conducting layer and at least one internal conducting layer, the first conducting layer having a plurality of electrode pads in a mounting region, the at least one internal conducting layer overlapping with the mounting region in a planar view, wherein a total area of one of the at least one internal conducting layer overlapping with the mounting region is in a range of 60% to 95% of an area of the mounting region in the planar view, and
the plurality of insulating layers having a first insulating layer, the first insulating layer being interposed between the first conducting layer and the internal conducting layer, the mounting region being defined on the first insulating layer.

2. The mounting component according to claim 1 ,
wherein the internal conducting layer includes a second conducting layer immediately below the first insulating layer, an area of the 2nd conducting layer overlapping with the electrode pads is in a range of 50% or more of the area of the electrode pads.

3. The mounting component according to claim 1 ,
wherein an area of the internal conducting layer overlapping with the mounting region is larger for conducting layers closer to the first conducting layer.

4. The mounting component according to claim 2 ,
wherein an area of the internal conducting layer overlapping with the mounting region is larger for conducting layers closer to the first conducting layer.

5. The mounting component according to claim 1 ,
wherein the plurality of conducting layers form a circuit pattern and does not form a dummy pattern.

6. The mounting component according to claim 5 ,
wherein the circuit pattern includes at least one of a signal pattern for transmitting a signal, a power supply pattern for maintaining a power supply potential, and a ground pattern for maintaining a ground potential.

7. The mounting component according to claim 1 ,
wherein the base material is silicon or glass.

8. An electronic device comprising:
a mounting component having a multilayer structure,
the multilayer structure having a plurality of conducting layers and a plurality of insulating layers alternately stacked on a base material, the plurality of conducting layer being connected by a plurality of interlayer connectors respectively,
the plurality of conducting layers having a first conducting layer and at least one internal conducting layer, the first conducting layer having a plurality of electrode pads in a mounting region, the at least one internal conducting layer overlapping with the mounting region in a planar view, wherein a total area of one of the at least one internal conducting layer overlapping with the mounting region is in a range of 60% to 95% of an area of the mounting region in the planar view, and
the plurality of insulating layers having a first insulating layer, the first insulating layer being interposed between the first conducting layer and the internal conducting layer, the mounting region being defined on the first insulating layer, and
a multilayer wiring substrate for flip-chip mounting the mounting component.

9. The electronic device according to claim 8 ,
wherein the internal conducting layer includes a second conducting layer immediately below the first insulating layer, an area of the 2nd conducting layer overlapping with the electrode pads is in a range of 50% or more of the area of the electrode pads.

10. The electronic device according to claim 8 ,
wherein an area of the internal conducting layer overlapping with the mounting region is larger for conducting layers closer to the first conducting layer.

11. The electronic device according to claim 9 ,
wherein an area of the internal conducting layer overlapping with the mounting region is larger for conducting layers closer to the first conducting layer.

12. The electronic device according to claim 8 ,
wherein the multilayer wiring substrate has the multilayer structure.

13. The electronic device according to claim 12 ,
wherein the internal conducting layer includes a second conducting layer immediately below the first insulating layer, an area of the 2nd conducting layer overlapping with the electrode pads is in a range of 50% or more of the area of the electrode pads.

14. The electronic device according to claim 12 ,
wherein an area of the internal conducting layer overlapping with the mounting region is larger for conducting layers closer to the first conducting layer.

15. The electronic device according to claim 13 ,
wherein an area of the internal conducting layer overlapping with the mounting region is larger for conducting layers closer to the first conducting layer.

16. The electronic device according to claim 12 , further comprising:
a gap exists between the mounting component and the multilayer wiring substrate, and
a conductive material arranged in the gap for connecting the electrode pads of the mounting component and the electrode pads of the multilayer wiring substrate.

17. The electronic device according to claim 16 , further comprising:
an insulating material arranged in the gap.

Assignees

• Dainippon Printing Co Ltd

Inventors

• Kasai Ryohei
• Tsunoda Tsuyoshi
• Yamamoto Yuichi
• SAGARA Shuji
• Tanaka Masaya

Classifications

• H05K1/097

  Inks comprising nanoparticles and specially adapted for being sintered at low temperature (H05K1/095 takes precedence) · CPC title

• H05K2201/10674

  Flip chip · CPC title

• H01L21/4867

  Electricity · mapped topic

• H01L21/4857

  Electricity · mapped topic

• H05K2201/0376

  Flush conductors, i.e. flush with the surface of the printed circuit · CPC title