Multilayer wiring substrate and module including same

Patent metadata

Field	Value
Publication number	US-9538644-B2
Application number	US-201414246266-A
Country	US
Kind code	B2
Filing date	Apr 7, 2014
Priority date	Apr 15, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A multilayer wiring substrate includes a multilayer body in which a plurality of insulating layers is stacked and to which an electronic component is mounted, a plurality of connection terminals disposed on one principal surface of the multilayer body for connection to the electronic component, and a plurality of rear electrodes disposed on the other principal surface of the multilayer body, wherein the connection terminals are each arranged in overlapped relation to one of the rear electrodes when looked at in a plan view of the multilayer wiring substrate.

First claim

What is claimed is:

1. A multilayer wiring substrate comprising:
a multilayer body in which a plurality of insulating layers is stacked and to which an electronic component is mounted;
a plurality of connection terminals disposed on one principal surface of the multilayer body for connection to the electronic component;
a plurality of rear electrodes disposed on another principal surface of the multilayer body; and
an in-plane conductor disposed inside the multilayer body on at least one of the insulating layers; wherein
the connection terminals are each arranged in overlapped relation to one of the rear electrodes when looked at in a plan view of the multilayer wiring substrate; and
a thickness of each of the rear electrodes is greater than a thickness of the in-plane conductor.

2. A module comprising the multilayer wiring substrate according to claim 1 , wherein
a plurality of outer terminals of the electronic component is disposed corresponding to two or more of the connection terminals of the multilayer body in the multilayer wiring substrate; and
the outer terminals of the electronic component are directly connected to the corresponding connection terminals.

3. The multilayer wiring substrate according to claim 1 , wherein the in-plane conductor is arranged in overlapped relation to all the connection terminals when looked at in the plan view.

4. The multilayer wiring substrate according to claim 1 , wherein
the in-plane conductor is disposed plural in at least two of the insulating layers;
at least two of the plural in-plane conductors include regions each overlapping with at least one of the connection terminals when looked at in the plan view; and
wiring densities in a stacking direction of the insulating layers in the regions of the in-plane conductors overlapping with the connection terminals are the same or substantially same.

5. The multilayer wiring substrate according to claim 1 , wherein the rear electrode arranged at a position overlapping with the connection terminal when looked at in the plan view is a ground electrode or a dummy electrode, the dummy electrode being not connected to any other electrodes.

6. The multilayer wiring substrate according to claim 1 , wherein the connection terminals are all arranged at positions overlapping with one of the rear electrodes when looked at in the plan view.

7. The multilayer wiring substrate according to claim 1 , wherein the connection terminals are disposed such that the electronic component is mounted in plural to the one principal surface.

8. The multilayer wiring substrate according to claim 1 , wherein the electronic component is one of a semiconductor element, a chip component, a chip capacitor, and a chip inductor.

9. The multilayer wiring substrate according to claim 5 , wherein the rear electrode that defines the ground electrode has a planar or substantially planar shape.

10. The multilayer wiring substrate according to claim 5 , wherein the rear electrode that defines the ground electrode overlaps all the connection terminals when looked at in the plan view.

11. The multilayer wiring substrate according to claim 1 , further comprising a framing configured to the rear electrodes from peeling off of the multilayer body.

12. The multilayer wiring substrate according to claim 1 , further comprising a plurality of in-plane conductors provided in the multilayer body such that at least two of the plurality of in-plane conductors is provided on a same one of the plurality of insulating layers.

13. The multilayer wiring substrate according to claim 1 , wherein the plurality of in-plane conductors overlap with respective ones of the plurality of connection terminals when looked at in the plan view.

14. The multilayer wiring substrate according to claim 1 , wherein the plurality of in-plane conductors are defined by ground conductors.

15. The multilayer wiring substrate according to claim 1 , wherein one of the plurality of rear electrodes overlaps at least two of the plurality of connection terminals when looked at in the plan view.

16. The multilayer wiring substrate according to claim 1 , wherein the plurality of connection terminals are arranged in a state straddling a region on the one principal surface of the multilayer body where there is a level difference in a stacking direction.

17. The module according to claim 2 , further comprising another electronic component mounted to a region on the one principal surface of the multilayer body that is not overlapped with any of the rear electrodes when looked at in the plan view, the other electronic component having a height greater than a height of the electronic component in a stacking direction.

Assignees

• Murata Manufacturing Co

Inventors

• Kitajima Hiromichi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H05K2201/0352

  Differences between the conductors of different layers of a multilayer · CPC title

• H05K1/0298 Primary

  Multilayer circuits · CPC title

• H05K2201/09672

  Superposed layout, i.e. in different planes · CPC title