Method for fabricating an electronic device and a stacked electronic device

US10672721B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10672721-B2
Application numberUS-201816208038-A
CountryUS
Kind codeB2
Filing dateDec 3, 2018
Priority dateNov 26, 2014
Publication dateJun 2, 2020
Grant dateJun 2, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method, comprising: fixing a rear face of an integrated-circuit chip to a front face of a support wafer; depositing on a front face of the integrated-circuit chip an infused adhesive in a form of drops or segments at a distance from one another and positioned outside a central region of the front face of the integrated-circuit chip, the infused adhesive comprising a curable adhesive and solid spacer elements infused in the curable adhesive; placing a protective wafer on the infused adhesive so that a free space remains between the front face of the integrated-circuit chip and a rear face of the protective wafer; curing the curable adhesive to fix the protective wafer to the integrated-circuit chip; producing an intermediate peripheral ring between the front face of the integrated-circuit chip and the rear face of the protective wafer after curing the curable adhesive; and producing an encapsulation ring around the integrated-circuit chip, the protective wafer, and the intermediate peripheral ring on a peripheral zone of the front face of the support wafer. 2. The method of claim 1 , wherein producing the intermediate peripheral ring comprises curing a resin using ultraviolet radiation without releasing gas. 3. The method of claim 1 , wherein producing the encapsulating ring comprises supplying a coating material and curing the coating material. 4. The method of claim 1 , wherein curing the curable adhesive comprises heating to polymerize the curable adhesive and releasing gas. 5. The method of claim 1 , wherein producing the encapsulation ring comprises applying a liquid material in an area which surrounds a stack formed by the integrated-circuit chip and the protective wafer. 6. The method of claim 5 , further comprising curing the liquid material and dicing the support wafer and the cured liquid material to form an electronic device. 7. The method of claim 1 , wherein the intermediate peripheral ring completely surrounds the free space. 8. The method of claim 1 , wherein the intermediate peripheral ring completely surrounds the protective wafer along a peripheral edge of the protective wafer. 9. The method of claim 8 , wherein the intermediate peripheral ring is produced to be in contact with the peripheral edge of the protective wafer.

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What does patent US10672721B2 cover?
A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer e…
Who is the assignee on this patent?
St Microelectronics Grenoble 2
What technology area does this patent fall under?
Primary CPC classification H01L23/562. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 02 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).