LDMOS transistor and method

Patent metadata

Field	Value
Publication number	US-10672686-B2
Application number	US-201916535237-A
Country	US
Kind code	B2
Filing date	Aug 8, 2019
Priority date	Jun 24, 2016
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

A method of forming a conductive through substrate via includes forming an opening in a first surface of a semiconductor substrate comprising a LDMOS transistor structure in the first surface, forming a first conductive layer in a first portion of the opening in the semiconductor substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion, and forming a second conductive layer on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer bounds a gap in the second portion.

First claim

What is claimed is:

1. A method, comprising:
forming an opening in a first surface of a semiconductor substrate comprising a LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor structure in the first surface;
forming a first conductive layer in a first portion of the opening in the semiconductor substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion; and
forming a second conductive layer on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer bounds a gap in the second portion,
wherein forming the opening comprises forming a trench having semiconductor sidewalls that extend from the first surface of the semiconductor substrate to a rear surface of the semiconductor substrate that is opposite from the first surface, and
wherein forming the first conductive layer comprises forming a conductive plug which completely fills the first portion and comprises an upper surface laterally extending between the semiconductor sidewalls of the trench, and
wherein forming the second conductive layer comprises conformally depositing the second conductive layer directly on the upper surface of the conductive plug and directly on the semiconductor sidewalls in the second portion of the opening.

2. The method of claim 1 , wherein the first deposition parameters are selected to favour growth of the first conductive layer in a vertical direction with respect to a major surface of the semiconductor substrate and the second deposition parameters are selected to favour growth of the second conductive layer in a lateral direction with respect to the major surface of the semiconductor substrate.

3. The method of claim 2 , wherein the first conductive layer and the second conductive layer are formed by electroplating.

4. The method of claim 1 , wherein the opening is a blind via, the first conductive layer is applied to a base of the blind via and the base of the blind via is filled with the first conductive layer.

5. The method of claim 4 , wherein the first conductive layer fills the blind via to a depth of 10% to 70% of a total depth of the blind via.

6. The method of claim 4 , further comprising working a second surface of the substrate and exposing a portion of the first conductive layer in the second surface of the substrate.

7. The method of claim 4 , further comprising:
applying a metallization structure to a front side of the semiconductor substrate; and
removing material from a rear side of the substrate to expose a surface of the first conductive layer.

8. The method of claim 1 , further comprising:
after applying the second conductive layer, capping the gap in the second portion of the opening.

9. The method of claim 1 , further comprising:
forming the second conductive layer on the first surface of the substrate surrounding the opening and on a conductive layer electrically coupled with an intrinsic source of the LDMOS transistor to electrically couple the intrinsic source with the first conductive layer.

10. The method of claim 1 , further comprising:
forming a first insulating layer over the second conductive layer that surrounds the gap; and
forming a second insulating layer over the gap so as to form an enclosed cavity within the opening.

11. The method of claim 1 , wherein the conductive plug comprises a rear surface which is coplanar with the rear surface of the semiconductor substrate and opposite from the upper surface.

12. A method, comprising:
providing a semiconductor substrate; and
forming a conductive through substrate via extending from a front surface to a rear surface of the semiconductor substrate,
wherein the conductive through substrate via comprises:
a conductive plug filling a first portion of the via, and
a conductive liner layer lining side walls of a second portion of the via and electrically coupled to the conductive plug,
wherein the through substrate via is formed between semiconductor sidewalls that vertically extend between the front and rear surfaces of the semiconductor substrate,
wherein the conductive plug comprises an upper surface laterally extending between the semiconductor sidewalls and a rear surface which is coplanar with the rear surface of the semiconductor substrate and opposite from the upper surface,
wherein vertical portions of the conductive liner layer vertically extend from the front surface to the upper surface of the conductive plug along the semiconductor sidewalls, and
wherein a lateral portion of the conductive liner laterally extends between the semiconductor sidewalls along the upper surface of the conductive plug.

13. The method of claim 12 , wherein forming the conductive through substrate via comprises:
forming a trench that extends from the front surface into the semiconductor substrate;
completely filling a bottom region of the trench with a first conductive layer thereby forming the conductive plug; and
conformally depositing a second conductive layer on the semiconductor substrate thereby forming the conductive liner layer.

Assignees

• Infineon Technologies Ag

Inventors

• Birner Albert
• Brech Helmut
• Zigldrum Matthias

Classifications

• H01L21/7682

  Electricity · mapped topic

• H01L21/76834

  Electricity · mapped topic

• H01L29/1045

  Electricity · mapped topic

• H01L21/2885

  Electricity · mapped topic

• H01L21/76846

  Electricity · mapped topic