Link width scaling across multiple retimer devices

Patent metadata

Field	Value
Publication number	US-10671553-B2
Application number	US-201715858366-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Dec 29, 2017
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

Differing widths of retimers are developed using differing numbers of individual retimer elements combined together. To maintain synchronous operation, various signals are provided between the individual retimer elements to allow synchronization of the various operations. A first signal is a wired-OR signal that is used for event and operation synchronization. A second set of signals form a serial bus used to transfer proper state information and operation correction data from a master retimer element to slave timer elements. The combination of the wired-OR signal and the serial bus allow the various state machines and operations inside each retimer element to be synchronized, so that the entire width of the link is properly synchronized.

First claim

The invention claimed is:

1. A processing device comprising:
a first processing element containing a plurality of first state machines which control operation of the first processing element and including:
a first calibration input/output for connection to a wired-OR calibration line; and
a first serial bus endpoint for connection to a serial bus, the serial bus including a serial bus clock and a serial data line for providing state data,
wherein the first calibration input/output receives indications from and provides indications to the plurality of first state machines and the first serial bus endpoint provides indications to the plurality of first state machines,
wherein at least one of the plurality of first state machines provide indication to the first calibration input/out that the first state machine is operating in a specific state, and
wherein at least one of the plurality of first state machines transition based on indications from the first calibration input/output and at least one of the plurality of first state machines transition based on state data provided on the serial bus; and

a second processing element containing a plurality of second state machines which control operation of the second processing element and including:
a second calibration input/output for connection to a wired-OR calibration line; and
a second serial bus endpoint for connection to a serial bus, the serial bus including a serial bus clock and a serial data line for providing state data,
wherein the second calibration input/output receives indications from and provides indications to the plurality of second state machines and the second serial bus endpoint provides indications to the plurality of second state machines,
wherein at least one of the plurality of second state machines provide indication to the second calibration input/out that the second state machine is operating in a specific state, and
wherein at least one of the plurality of second state machines transition based on indications from the second calibration input/output and at least one of the plurality of second state machines transition based on state data provided on the serial bus;

a wired-OR calibration line connected to the first and second calibration input/outputs; and
a serial bus including a serial bus clock and a serial data line, the serial bus connected to the first and second serial bus endpoints,
wherein the plurality of first state machines and the plurality of second state machines are instances of the same state machines in the respective first and second processing elements,
wherein the at least one of the plurality of first state machines and the at least one of the plurality of second state machines are instances of the same state machine in the respective first and second processing elements, and
wherein the at least one of the plurality of first state machines and the at least one of the plurality of second state machines transition together.

2. The processing device of claim 1 , wherein the first processing element is a master element,
wherein the first serial bus endpoint provides the serial bus clock and the state data on the serial data line,
wherein the second processing element is a slave element and wherein the second serial bus endpoint receives the serial bus clock and the state data on the serial data line.

3. The processing device of claim 1 , wherein the first and second processing elements are link retimers.

4. The processing device of claim 3 , wherein the serial data line further provides condition data, and
wherein one of the first and second processing element uses the condition data to perform an operation.

5. The processing device of claim 1 , wherein the serial data line further provides operation correction data and wherein one of the first and second processing elements uses the operation correction data to correct an operation.

6. The processing device of claim 1 , wherein the first processing element includes a first clock driver providing a clocking signal,
wherein the first calibration input/output synchronizes the clocking signal provided by the first clock driver,
wherein the second processing element includes a second clock driver providing a clocking signal, and
wherein the second calibration input/output synchronizes the clocking signal provided by the second clock driver.

Assignees

• Texas Instruments Inc
• Texas Instuments Incorporated

Inventors

• Leung Pakyiu
• Morrison Casey Thomas

Classifications

• G06F13/4295

  using an embedded synchronisation · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F13/1678 Primary

  using bus width · CPC title