Method, device and system for analog-to-digital conversion

Patent metadata

Field	Value
Publication number	US-10666281-B2
Application number	US-201916386699-A
Country	US
Kind code	B2
Filing date	Apr 17, 2019
Priority date	Apr 20, 2018
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

In accordance with an embodiment, a method for calibrating at least two analog-to-digital converters includes feeding an analog predefined signal to the at least two analog-to-digital converters; converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on a received clock signal; and adapting a converter-specific time delay based on the at least two converter-associated digital values.

First claim

What is claimed is:

1. A method for calibrating at least two analog-to-digital converters, wherein the at least two analog-to-digital converters each receive a clock signal, and at least one of the at least two analog-to-digital converters receives the clock signal with a converter-specific time delay, the method comprising:
feeding an analog predefined signal to the at least two analog-to-digital converters, wherein the analog predefined signal is at least one of
a periodic signal, or
at least in sections is a strictly monotonically rising signal or a strictly monotonically falling signal;

converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on the received clock signal; and
adapting the converter-specific time delay based on the at least two converter-associated digital values.

2. The method as claimed in claim 1 , wherein the method further comprises decreasing the converter-specific time delay when the converter-specific time delays reaches a maximum value; or
increasing all the converter-specific time delay when the converter-specific time delays reaches a minimum value.

3. The method as claimed in claim 1 , wherein the periodic signal comprises a first signal section and a second signal section, and wherein the periodic signal is strictly monotonically rising in the first signal section.

4. The method as claimed in claim 3 , wherein the periodic signal is strictly monotonically falling in the second signal section.

5. The method as claimed in claim 3 , wherein the analog predefined signal is substantially linear in the first signal section or in the second signal section.

6. The method as claimed in claim 5 , wherein the at least two analog-to-digital converters comprise at least three analog-to-digital converters, which each receive the clock signal with a respective converter-specific time delay, and wherein:
calibration is performed during a substantially linear signal section,
a respective difference between the converter-associated value of the respective converter and the converter-associated value of a respective previous analog-to-digital converter is formed,
an average value is formed from the converter-associated differences,
the converter-associated differences are compared with the average value,
adapting comprises reducing the converter-specific delay when the converter-associated difference is greater than the average value.

7. The method as claimed in claim 1 , wherein adapting the converter-specific time delay is based on a multiplicity of conversions over a multiplicity of periods of the analog predefined signal.

8. The method as claimed in claim 7 , wherein
at least two of the at least two analog-to-digital converters receive the clock signal with a respective converter-specific time delay;
wherein the multiplicity of conversions over at least two periods of the analog predefined signal comprises a permutation of the respective converter-specific time delays between at least two of the multiplicity of periods of the analog predefined signal; and
wherein the adapting the at least two respective converter-specific time delays is based on an averaging of the converter-associated digital values over the at least two periods of the analog predefined signal.

9. The method as claimed in claim 8 , wherein adapting the at least two converter-specific time delays is based on:
at least one first difference ascertained based on the two converter-associated digital values in at least one first period of the analog predefined signal; and
a second difference ascertained based on the two converter-associated digital values in at least one second period of the analog predefined signal.

10. The method of claim 1 , further comprising generating the analog predefined signal based on a control signal.

11. The method as claimed in claim 1 , wherein adapting the converter-specific time delay is based on a comparison of the at least two converter-associated digital values with a known characteristic of the analog predefined signal.

12. The method as claimed in claim 1 , wherein:
the method is performed for a repeated number of times;
wherein for each time the method is performed, the at least two analog-to-digital converters are selected from an arrangement of at least three analog-to-digital converters; and
wherein the adapting is carried out based on the at least two converter-associated values from performing the method the repeated number of times.

13. A buffer circuit comprising:
at least one buffer input for at least one analog signal, at least one calibration control input, and at least one analog output, wherein the buffer circuit comprises at least one operational amplifier having a first set of terminals, the first set of terminals comprising a first terminal and a second terminal, and wherein the buffer circuit is configured to operate in at least the following operating modes:
a buffer operating mode, wherein the buffer circuit is configured, in reaction to a received first signal at the at least one calibration control input, to connect at least one resistor between the first terminal of the at least one operational amplifier and the second terminal of the at least one operational amplifier such that the at least one analog signal is received at the at least one buffer input and is provided at the at least one analog output, and
a calibration operating mode, wherein the buffer circuit is configured, in reaction to a received second signal at the at least one calibration control input, to connect at least one capacitance between the first terminal and the second terminal of the at least one operational amplifier and to connect a reset switch in parallel with the at least one capacitance and also to connect at least one current source to the first input of the at least one operational amplifier.

14. The buffer circuit as claimed in claim 13 , wherein the buffer circuit comprises a second current source, wherein the second current source is coupled to the first current source by an arrangement of switches, wherein the arrangement of switches is configured to reverse a polarity of the signal generated in the calibration operating mode by actuating at least two switches of the arrangement of switches.

15. The buffer circuit as claimed in claim 13 , wherein the at least one operational amplifier is a differential operational amplifier further comprising a third terminal and a fourth terminal.

16. A device comprising:
at least two analog-to-digital converters,
wherein the at least two analog-to-digital converters are configured to receive a respective clock signal, wherein at least one of the analog-to-digital converters is coupled to a converter-specific time delay circuit configured to provide for the at least one analog-to-digital converter the clock signal with a converter-specific time delay, and the at least two analog-to-digital converters are configured to convert a received analog input signal into converter-associated digital values, and
wherein the at least two analog-to-digital converters are configured to receive an analog predefined signal as the analog input signal, wherein the analog predefined signal is at least one of
a periodic signal, or
at least in sections is a strictly monotonically rising signal or a strictly monotonically falling signal; and

a control circuit configured to receive the converter-associated digital values generated in response to the analog predefined signal and to perform an adaptation of a set

Assignees

• Infineon Technologies Ag

Inventors

• Pernull Martin
• Bogner Peter

Classifications

• H03M1/0836 Primary

  of phase error, e.g. jitter · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H03M1/1033 Primary

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/1019

  by storing a corrected or correction value in a digital look-up table · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title