Analog-to-digital converter (ADC) having calibration

Patent metadata

Field	Value
Publication number	US-10243577-B1
Application number	US-201815943173-A
Country	US
Kind code	B1
Filing date	Apr 2, 2018
Priority date	Apr 2, 2018
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

An analog-to-digital converter (ADC) includes a split-capacitor digital-to-analog converter (DAC) having a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs, and coupled to receive an analog input voltage, a high reference voltage, and a low reference voltage, and to provide an output voltage. The ADC includes a comparator coupled to receive the output voltage, successive-approximation-register (SAR) circuitry coupled to the comparator and providing an uncalibrated digital value corresponding to an uncalibrated digital representation of the input voltage, and calibration circuitry configured to apply one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC) comprising:
a split-capacitor digital-to-analog converter (DAC) having a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs, and coupled to receive an analog input voltage, a high reference voltage, and a low reference voltage, and to provide an output voltage, wherein the high reference voltage is greater than the low reference voltage;
a comparator having a first input coupled to receive the output voltage of the DAC, a second input, and a comparison output based on a difference in voltage between the first input and the second input;
successive-approximation-register (SAR) circuitry having an input coupled to receive the comparison output, and an output to provide an uncalibrated digital value corresponding to an uncalibrated digital representation of the input voltage; and
calibration circuitry coupled to receive the uncalibrated digital value and configured to apply one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the input voltage, wherein the calibration values are selected based on the value of MSBs of the uncalibrated digital value.

2. The ADC of claim 1 , wherein the calibration circuitry is configured to obtain a calibration value corresponding to each binary capacitor and each thermometer capacitor of the MSBs sub-DAC.

3. The ADC of claim 2 , wherein the calibration circuitry is configured to obtain a calibration value, for each thermometer capacitor of the one or more thermometers capacitors, by individually comparing a capacitance of the thermometer capacitor to a sum of all capacitances of all binary capacitors and all capacitors of the LSBs sub-DAC and the termination capacitor.

4. The ADC of claim 3 , wherein the calibration circuitry is configured to obtain a corresponding calibration value, for each binary capacitor, by comparing a capacitance of the binary capacitor to a sum of capacitances of all capacitors of lesser significant bits than the binary capacitor, including all capacitors of the LSBs sub-DAC, and the termination capacitor.

5. The ADC of claim 4 , wherein the calibration circuitry is configured to apply the one or more calibration values to the uncalibrated digital value when the value of the MSBs of the uncalibrated digital value is greater than 0.

6. The ADC of claim 5 , wherein the calibration circuitry is configured to apply the one or more calibration values to the uncalibrated digital value by subtracting at least N times the calibration value corresponding to the least significant binary capacitor of the one or more binary capacitors when the value of the MSBs of the uncalibrated digital value is greater than 0, wherein N is an integer greater than 0.

7. The ADC of claim 6 , wherein the calibration circuitry is configured to apply the one or more calibration values to the uncalibrated digital value by also subtracting the calibration value corresponding to the least significant thermometer capacitor of the one or more thermometer capacitors when the value of the MSBs of the uncalibrated signal is greater than one less than 2 raised to a number of binary capacitors of the one or more binary capacitors.

8. The ADC of claim 4 , wherein the calibration circuitry is configured to store each calibration value.

9. The ADC of claim 4 , wherein the calibration circuitry is configured to store sums of selected calibration values.

10. The ADC of claim 1 , wherein the calibration circuitry is configured to, during calibration, for each thermometer capacitor:
during a sample phase, provide DAC control signals to the DAC to charge the thermometer capacitor by coupling the thermometer capacitor to the low reference voltage and coupling all lower significant capacitors the high reference voltage; and
during a comparison phase, provide the DAC control signals to couple the thermometer capacitor to the high reference voltage and couple the one or more binary capacitors and all lower significance capacitors of the DAC to the low reference voltage.

11. The ADC of claim 10 , wherein the SAR circuitry is configured to, during calibration, for each thermometer capacitor, perform successive-approximation on the comparison output of the comparator to obtain the calibration value for the thermometer capacitor.

12. The ADC of claim 11 , wherein the ADC is configured to, during the sample phase, charge the first and second inputs of the comparator to a common mode voltage, and prior to commencing the comparison phase, release the first and second inputs of the comparator.

13. The ADC of claim 1 , wherein the calibration circuitry is configured to, during calibration, for each binary capacitor:
during a sample phase, provide DAC control signals to the DAC to charge the binary capacitor by coupling the binary capacitor to the low reference voltage and coupling all lower significance capacitors of the DAC to the high reference voltage; and
during a comparison phase, provide the DAC control signals to the DAC to couple the binary capacitor to the high reference voltage and couple all lower significance capacitors of the DAC to the low reference voltage.

14. The ADC of claim 1 , wherein each bit of the uncalibrated digital representation is based on a corresponding value of the comparison output.

15. In an analog-to-digital converter (ADC), a method comprising:
providing an analog input voltage to a split-capacitor digital-to-analog converter (DAC) within the ADC, wherein the DAC includes a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs;
performing a comparison using an output of the DAC to provide a comparison output;
performing a successive-approximation on the comparison output to provide an uncalibrated digital value which represents an input voltage to the DAC;
obtaining a calibration value corresponding to each binary capacitor and each thermometer capacitor of the MSBs sub-DAC, wherein the obtaining the calibration value corresponding to each thermometer capacitor comprises:
for each thermometer capacitor:
during a sample phase, charging the thermometer capacitor by coupling the thermometer capacitor to the low reference voltage and coupling all lower significant capacitors the high reference voltage;
during a comparison phase, coupling the thermometer capacitor to the high reference voltage and coupling the one or more binary capacitors and all lower significance capacitors of the DAC to the low reference voltage; and
performing successive-approximation on the output of the comparator to obtain the calibration value for the thermometer capacitor; and

using one or more calibration values to adjust the uncalibrated digital value to obtain a calibrated digital representation of the input voltage, wherein the one or more calibration values are selected based on the value of MSBs of the uncalibrated digital value.

16. The method of claim 15 , wherein the obtaining a calibration value corresponding to each binary capacitor and each thermometer capacitor of

Assignees

• Nxp Usa Inc

Inventors

• Berens Michael Todd
• Mai Khoi
• Feddeler James Robert

Classifications

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/1047 Primary

  using an auxiliary digital/analogue converter for adding the correction values to the analogue signal (H03M1/1052 takes precedence) · CPC title

• H03M1/1042 Primary

  the look-up table containing corrected values for replacing the original digital values (H03M1/1052 takes precedence) · CPC title