Coarse grid design methods and structures
US-9917056-B2 · Mar 13, 2018 · US
US10658385B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10658385-B2 |
| Application number | US-201313831636-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 15, 2013 |
| Priority date | Mar 13, 2008 |
| Publication date | May 19, 2020 |
| Grant date | May 19, 2020 |
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A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a third gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a fourth gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.
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What is claimed is: 1. A cross-coupled transistor circuit, comprising: a first PMOS transistor defined by a gate electrode extending along a first gate electrode track; a second PMOS transistor defined by a gate electrode extending along a second gate electrode track; a first NMOS transistor defined by a gate electrode extending along a third gate electrode track; a second NMOS transistor defined by a gate electrode extending along a fourth gate electrode track, wherein th…
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