Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9356038-B2
Application number	US-201414465573-A
Country	US
Kind code	B2
Filing date	Aug 21, 2014
Priority date	Mar 6, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes insulating layers stacked in the shape of stairs, and conductive layers alternately stacked with the insulating layers, wherein the conductive layers each include a first region interposed between upper and lower insulating layers thereof, among the insulating layers, and a second region which extends from the first region and protrudes between the upper and lower insulating layers, and wherein a protruding part formed on a sidewall or an upper surface of the second region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
insulating layers stacked in the shape of stairs; and
conductive layers alternately stacked with the insulating layers,
wherein the conductive layers each include a first region interposed between upper and lower insulating layers thereof, among the insulating layers, and a second region which extends from the first region and protrudes between the upper and lower insulating layers, and
wherein a protruding part is formed on a sidewall of the second region.

2. The semiconductor device of claim 1 , further comprising:
a first undercut formed between the protruding part of each of the conductive layers and the lower insulating layer thereof.

3. The semiconductor device of claim 2 , further comprising:
a liner layer formed on the conductive layers and the insulating layers to fill the first undercut.

4. The semiconductor device of claim 3 , further comprising:
contact plugs connected to second regions of the conductive layers and passing through the liner layer.

5. The semiconductor device of claim 1 , further comprising:
a groove formed between the second region of each of the conductive layers and the upper insulating layer corresponding thereto.

6. The semiconductor device of claim 1 , further comprising:
an insulating pattern formed on the second region of each of the conductive layers; and
a second undercut formed between the protruding part of each of the conductive layers and the insulating pattern corresponding thereto.

7. The semiconductor device of claim 1 , further comprising:
an insulating pattern formed on the second region of each of the conductive layers; and
contact plugs connected to second regions of the conductive layers and passing through the insulating pattern.

8. The semiconductor device of claim 1 , further comprising:
semiconductor patterns formed to pass through first regions of the conductive layers and the insulating layers.

9. The semiconductor device of claim 1 , wherein the second region of each of the conductive layers has a greater thickness than the first region thereof.

10. The semiconductor device of claim 1 , wherein the protruding part of each of the conductive layers is formed to extend from the upper surface of the second region thereof.

11. The semiconductor device of claim 1 , wherein the protruding part of each of the conductive layers is formed in a center of the sidewall of the second region thereof.

12. The semiconductor device of claim 1 , wherein the upper surface of the second region of each of the conductive layers is formed at a level equal to or lower than an upper surface of the upper insulating layer corresponding thereto.

13. The semiconductor device of claim 1 , wherein the first region of each of the conductive layers is a word line, and the second region thereof is a pad part.

14. The semiconductor device of claim 1 , wherein the protruding part is formed on the sidewall and an upper surface of the second region.

15. A semiconductor device, comprising:
insulating layers stacked in the shape of stairs; and
conductive layers alternately stacked with the insulating layers, wherein the conductive layers each include a pad part protruding between upper and lower insulating layers thereof, among the insulating layers, in a shape of a bird's beak.

16. The semiconductor device of claim 15 , further comprising:
a liner layer formed on the insulating layers and the conductive layers to cover the pad part of each of the conductive layers.

17. The semiconductor device of claim 16 , further comprising:
contact plugs connected to the conductive layers and passing through the liner layer.

18. The semiconductor device of claim 15 , further comprising:
a first undercut formed between the pad part of each of the conductive layers and the lower insulating layer corresponding thereto.

19. The semiconductor device of claim 15 , further comprising:
a groove formed between the pad part of each of the conductive layers and the upper insulating layer corresponding thereto;
an insulating pattern formed on the pad part of each of the conductive layers; and
a second undercut formed between the pad part of each of the conductive layers and the insulating pattern corresponding thereto.

20. The semiconductor device of claim 15 , wherein the pad part of each of the conductive layers has a greater thickness than other parts thereof.

Assignees

• Sk Hynix Inc

Inventors

• Lee Ki Hong
• Pyi Seung Ho
• Jeon Seok Min

Classifications

• H01L27/11548

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11575 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10B41/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title