Vertical type semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9293172-B2
Application number	US-201313865580-A
Country	US
Kind code	B2
Filing date	Apr 18, 2013
Priority date	Jul 17, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced.

First claim

What is claimed is:

1. A vertical type semiconductor device, comprising:
a pillar structure protruding in a vertical direction from a surface of a substrate in a cell array region and including a channel pattern;
lower word lines surrounding the pillar structure formed in the cell array region, wherein the lower word lines are stacked and spaced apart from each other in the vertical direction;
upper word lines surrounding the pillar structure formed in the cell array region, wherein the upper word lines are disposed over the lower word lines;
a MOS transistor on the substrate of a peripheral circuit region;
a first insulating interlayer pattern on the substrate of the peripheral circuit region to cover the MOS transistor;
a second insulating interlayer pattern on the substrate of the cell array region to cover the lower word lines, wherein top surfaces of the first and second insulating interlayer patterns are substantially coplanar with each other;
a third insulating interlayer pattern directly on the first and second insulating interlayer patterns to cover the upper word lines;
a first contact plug passing through the first insulating interlayer pattern;
a second contact plug passing through the second insulating interlayer pattern; and
a third contact plug directly contacting a top surface of the first contact plug, and passing through the third insulating interlayer pattern, wherein a bottom surface of the third contact plug is lower than a top surface of an upper most word line of the upper word lines.

2. The vertical type semiconductor device of claim 1 , wherein the first contact plug includes a plurality of first contact plugs, and the first contact plugs are electrically connected to a source region, a drain region and a gate of the MOS transistor, respectively.

3. The vertical type semiconductor device of claim 1 , wherein the second contact plug includes a plurality of second contact plugs, and the second contact plugs contact the lower word lines, respectively.

4. The vertical type semiconductor device of claim 1 , wherein the first and second contact plugs include substantially the same material.

5. The vertical type semiconductor device of claim 1 , wherein the top surfaces of the first and second contact plugs are substantially coplanar with each other.

6. The vertical type semiconductor device of claim 1 , wherein top surfaces of the first and second insulating interlayer patterns are substantially coplanar with each other.

7. The vertical type semiconductor device of claim 1 , further comprising fourth contact plugs directly contacting the upper word lines and top surfaces of the second contact plugs, respectively, and passing through the third insulating interlayer pattern.

8. The vertical type semiconductor device of claim 7 , wherein the third and fourth contact plugs include substantially the same material.

9. The vertical type semiconductor device of claim 7 , wherein top surfaces of the third and fourth contact plugs are substantially coplanar with each other.

10. The vertical type semiconductor device of claim 1 , wherein a top surface of the third insulating interlayer pattern is higher than a top surface of the pillar structure.

11. The vertical type semiconductor device of claim 1 , wherein a sidewall of the pillar structure is not bent in a horizontal direction.

12. The vertical type semiconductor device of claim 1 , wherein the pillar structure further include a tunnel insulating layer pattern, a charge trap layer pattern and a dielectric layer pattern which are stacked on the channel pattern in a horizontal direction.

13. The vertical type semiconductor device of claim 1 , wherein the first, second and third insulating interlayer patterns include first, second and third insulating materials, respectively, and the first, second and third insulating materials are formed by different deposition processes, respectively.

14. A vertical type semiconductor device, comprising:
a pillar structure protruding in a vertical direction from a surface of a substrate in a cell array region and including a channel pattern, a tunnel insulating layer pattern, a charge trap pattern and a dielectric layer pattern which are stacked in a horizontal direction;
lower word lines surrounding the pillar structure, wherein the lower word lines are stacked and spaced apart from each other in the vertical direction;
upper word lines surrounding the pillar structure, wherein the upper word lines are disposed over the lower word lines;
a first insulating interlayer pattern provided on the substrate in a peripheral circuit region, the first insulating interlayer pattern having a top surface positioned between the upper and lower word lines;
a second insulating interlayer pattern on the substrate of the cell array region to cover the lower word lines, wherein top surfaces of the first and second insulating interlayer patterns are substantially coplanar with each other;
a third insulating interlayer pattern directly on the first and second insulating interlayer patterns to cover the upper word lines;
a first contact plug contacting the surface of the substrate in the peripheral circuit region, and passing through the first insulating interlayer pattern;
second contact plugs contacting the lower word lines, and passing through the second insulating interlayer pattern;
a third contact plug directly contacting a top surface of the first contact plug, and passing through the third insulating interlayer pattern, wherein a bottom surface of the third contact plug is lower than a top surface of an upper most word line of the upper word lines; and
fourth contact plugs directly contacting the upper word lines and top surfaces of the second contact plugs, respectively, and passing through the third insulating interlayer pattern.

15. The vertical type semiconductor device of claim 14 , wherein the first insulating interlayer covers a MOS transistor on the substrate in the peripheral circuit region.

16. The vertical type semiconductor device of claim 14 , wherein the first and second contact plugs include substantially the same material.

17. The vertical type semiconductor device of claim 14 , wherein the top surfaces of the first and second contact plugs are substantially coplanar with each other.

18. The vertical type semiconductor device of claim 14 , wherein the third and fourth contact plugs include substantially the same material.

19. The vertical type semiconductor device of claim 14 , wherein a top surface of the third insulating interlayer pattern is higher than a top surface of the pillar structure.

20. The vertical type semiconductor device of claim 14 , wherein the first, second and third insulating interlayer patterns include first, second and third insulating materials, respectively, and the first, second and third insulating materials are formed by different deposition processes, respectively.

Assignees

• Lee Jae-Goo
• Lim Jin-Soo
• Samsung Electronics Co Ltd

Inventors

• Lee Jae-Goo
• Lim Jin-Soo

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L21/76816

  Electricity · mapped topic