Silicon-based deposition for semiconductor processing

Patent metadata

Field	Value
Publication number	US-10658194-B2
Application number	US-201615244311-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Aug 23, 2016
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A method for processing a substrate in a processing chamber, comprising forming a deposition over the substrate is provided. A silicon containing gas is flowed into the processing chamber. A COS containing gas is flowed into the processing chamber. A plasma is formed from the silicon containing gas and the COS containing gas in the processing chamber, wherein the plasma provides the deposition over the substrate.

First claim

What is claimed is:

1. A method for processing a substrate in a processing chamber, wherein a stack of a plurality of alternating layers is over the substrate, and wherein at least one of the alternating layers is silicon oxide, comprising:
partially etching features in the plurality of alternating layers of the stack;
after partially etching features, forming a deposition on sidewalls of the partially etched features in the plurality of alternating layers, comprising:
flowing a silicon containing gas into the processing chamber;
flowing a COS containing gas into the processing chamber;
providing RF power into the processing chamber from at least one transformer coupled plasma (TCP) coil; and
forming a plasma from the silicon containing gas and the COS containing gas in the processing chamber using the RF power, wherein the plasma provides the deposition on sidewalls of the partially etched features in the plurality of alternating layers; and

after forming the deposition on sidewalls of the partially etch features is completed, further etching the partially etched features in the plurality of alternating layers of the stack, wherein the deposition protects sidewalls of the partially etched features from the further etching.

2. The method, as recited in claim 1 , wherein the deposition comprises silicon, oxygen, and sulfur.

3. The method, as recited in claim 2 , wherein the deposition further comprises carbon.

4. The method, as recited in claim 3 , wherein the silicon containing gas and COS containing gas are provided cyclically for a plurality of cycles, wherein there is some mixing between the silicon containing gas and the COS containing gas.

5. The method, as recited in claim 1 , further comprising removing the deposition.

6. The method, as recited in claim 5 , wherein the removing the deposition, comprises:
providing a removal gas comprising a halogen containing component and O 2 ; and
forming a plasma from the removal gas, which removes the deposition.

7. The method, as recited in claim 1 , wherein the silicon containing gas comprises at least one of SiH 4 , SiF 4 , SiCl 4 , SiH x F y , SiH x Cl y , SiF x Cl y , wherein x and y are positive integers and x+y=4.

8. The method, as recited in claim 1 , wherein the silicon containing gas and COS containing gas are provided simultaneously.

9. The method, as recited in claim 1 , wherein the silicon containing gas and COS containing gas are provided sequentially, wherein there is some mixing between the silicon containing gas and the COS containing gas.

10. The method, as recited in claim 1 , wherein the silicon containing gas and COS containing gas are provided cyclically for a plurality of cycles, wherein there is some mixing between the silicon containing gas and the COS containing gas.

11. The method, as recited in claim 1 , wherein the forming the plasma provides the deposition for a period of between 5 to 100 seconds.

12. The method, as recited in claim 1 , wherein the stack further comprises a patterned mask over the plurality of alternating layers, wherein the patterned mask is a carbon hardmask and wherein the carbon hardmask provides a mask for the partial etching partially etching features and further etching the partially etched features.

13. The method, as recited in claim 12 , wherein the memory stack is an oxide, nitride, oxide nitride (ONON) memory stack.

Assignees

• Lam Res Corp

Inventors

• Tan Zhongkui
• Xu Qing
• Fu Qian
• Xiang Hua
• Zhao Lin

Classifications

• C23C16/45544

  characterized by the apparatus · CPC title

• C23C16/50

  using electric discharges {(generation and control of plasma in discharge tubes for surface treatment H01J37/32, H01J37/34)} · CPC title

• H01J37/32009

  Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources (plasma generation in general H05H1/24) · CPC title

• C23C16/52

  Controlling or regulating the coating process {(C23C16/45557, C23C16/279 take precedence)} · CPC title

• H01J37/32449

  Gas control, e.g. control of the gas flow · CPC title