Chip handling and electronic component integration

Patent metadata

Field	Value
Publication number	US-10658182-B2
Application number	US-201916551377-A
Country	US
Kind code	B2
Filing date	Aug 26, 2019
Priority date	Sep 20, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.

First claim

What is claimed is:

1. A method for integrating electronic elements into an electronic package assembly, comprising:
obtaining a semiconductor structure including a device wafer comprising an array of singulated electronic elements, a handle wafer, and a release layer, the device wafer being bonded to the handle wafer, and the release layer being positioned between the device wafer and the handle wafer;
aligning a carrier with the device wafer, the carrier including a rigid body portion and a plurality of discrete raised regions extending from the rigid body portion, each of the discrete raised regions corresponding to one of a targeted plurality of the singulated electronic elements;
depositing a further release layer on a top surface of the device wafer or on the raised regions of the carrier;
attaching the targeted plurality of singulated electronic elements to the discrete raised regions of the carrier;
subsequent to attaching the targeted plurality of the singulated electronic elements to the discrete raised regions of the carrier and while maintaining attachment of the of the targeted plurality of singulated electronic elements to the discrete raised regions of the carrier, directing electromagnetic radiation through the handle wafer, thereby causing ablation of discrete, selected portions of the release layer beneath the targeted plurality of the singulated electronic elements;
aligning the targeted plurality of singulated electronic elements attached to the carrier with a plurality of targeted bonding sites of an electronic package assembly;
integrating the targeted plurality of singulated electronic elements into the electronic package assembly at the targeted bonding sites, and
detaching the targeted plurality of singulated electronic elements from the discrete raised regions of the carrier.

2. The method of claim 1 , further including:
removing portions of the release layer between the singulated electronic elements prior to causing ablation of the discrete, selected portions of the release layer beneath the targeted plurality of the singulated electronic elements.

3. The method of claim 1 , further including:
bonding the targeted plurality of singulated electronic elements to the carrier using the further release layer prior to causing ablation of the discrete, selected portions of the release layer.

4. The method of claim 1 , wherein causing ablation of the discrete, selected portions of the release layer includes subjecting the release layer to radiation in the UV range.

5. The method of claim 1 ,
further wherein detaching the targeted plurality of the singulated electronic elements from the discrete raised regions of the carrier includes ablating the further release layer by directing electromagnetic radiation through the carrier, the frequency of the electromagnetic radiation directed through the carrier being different from the frequency of the electromagnetic radiation directed through the handle wafer.

6. The method of claim 5 , wherein depositing the further release layer includes depositing the further release layer on the device wafer and patterning the further release layer on the device wafer to correspond to the targeted plurality of the singulated electronic elements.

7. The method of claim 1 , wherein the singulated electronic elements include solder bump arrays, and further wherein integrating the targeted plurality of singulated electronic elements into the electronic package assembly includes reflow of the solder bump arrays, thereby bonding the targeted plurality of the singulated electronic elements to the targeted bonding sites of the electronic package assembly.

8. The method of claim 1 , further including forming a patterned mask on the handle wafer including openings aligned with the targeted plurality of the singulated electronic elements and directing the electromagnetic radiation through the openings in the patterned mask.

9. The method of claim 1 , wherein directing electromagnetic radiation through the handle wafer includes causing a laser scanning system to sequentially generate electromatic radiation pulses and direct the electromatic radiation energy to areas or spots corresponding to the targeted plurality of the singulated electronic elements, thereby sequentially causing the ablation of the discrete, selected portions of the release layer beneath the targeted plurality of singulated electronic elements.

10. The method of claim 1 , wherein obtaining the semiconductor structure includes:
bonding the device wafer to the handle wafer using the release layer and a distinct adhesive layer, the distinct adhesive layer being positioned between the release layer and the device wafer, and
dicing the device wafer on the handle wafer, thereby forming the plurality of the singulated electronic elements.

11. The method of claim 10 , further including removing portions of the release layer and the distinct adhesive layer between the singulated electronic elements prior to causing ablation of the discrete, selected portions of the release layer beneath the targeted plurality of the singulated electronic elements.

12. The method of claim 1 , wherein the singulated electronic elements include solder bump arrays, and further wherein integrating the targeted plurality of singulated electronic elements into the electronic package assembly includes reflow of the solder bump arrays, thereby bonding the targeted plurality of the singulated electronic elements to the targeted bonding sites of the electronic package assembly.

13. The method of claim 12 , wherein bonding the targeted plurality of the singulated electronic elements to the targeted bonding sites is conducted prior to detaching the targeted plurality of singulated electronic elements from the carrier.

14. The method of claim 13 , wherein detaching the targeted plurality of the singulated electronic elements from the carrier includes ablating the further release layer by directing electromagnetic radiation through the carrier, the frequency of the electromagnetic radiation directed through the carrier being different from the frequency of the electromagnetic radiation directed through the handle wafer.

15. The method of claim 14 , wherein detaching the targeted plurality of the singulated electronic elements from the carrier further includes non-selectively releasing all of the targeted plurality of the singulated electronic elements from the carrier.

16. The method of claim 5 , wherein detaching the targeted plurality of the singulated electronic elements from the carrier further includes non-selectively releasing all of the targeted plurality of the singulated electronic elements from the carrier.

17. The method of claim 1 , wherein the further release layer is deposited on the raised regions of the carrier.

18. The method of claim 1 , wherein obtaining the semiconductor structure includes:
bonding the device wafer to the handle wafer;
thinning the device wafer on the handle wafer; and
dicing the device wafer subsequent to thinning.

19. The method of claim 18 , wherein obtaining the semiconductor structure further includes:
depositing an adhesive layer on the release layer or on the device wafer.

20. A method for integrating electronic elements into an electronic package assembly, comprising:
obtaining a semiconductor structure including a device wafer comprising an array of singulated electronic elements, a handle wafer, and a release layer, the device wafer being bonded to the handle wafer, and the release layer bein

Assignees

• IBM

Inventors

• Budd Russell A
• Chen Qianwen
• Dang Bing
• Gelorme Jeffrey D
• Hung Li-Wen
• Knickerbocker John U

Classifications

• B24B7/228

  for grinding thin, brittle parts, e.g. semiconductors, wafers (grinding edges of thin, brittle parts B24B9/065) · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10P72/7448

  the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

• H01L2221/68318

  Electricity · mapped topic