Cross-coupled transistor circuit defined on three gate electrode tracks

Patent metadata

Field	Value
Publication number	US-10651200-B2
Application number	US-201313831605-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 13, 2008
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

First claim

What is claimed is:

1. A cross-coupled transistor circuit, comprising:
a first PMOS transistor formed in part by a first gate electrode;
a second PMOS transistor formed in part by a second gate electrode;
a first NMOS transistor formed in part by a third gate electrode co-aligned with the second gate electrode;
a second NMOS transistor formed in part by a fourth gate electrode,
wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node,
wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node, and
wherein each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

2. A cross-coupled transistor circuit as recited in claim 1 , wherein the first PMOS transistor is positioned next to the second PMOS transistor.

3. A cross-coupled transistor circuit as recited in claim 1 , wherein the first NMOS transistor is positioned next to the second NMOS transistor.

4. A cross-coupled transistor circuit as recited in claim 1 , wherein each of the first, second, and third gate electrodes extend in a first direction.

5. A cross-coupled transistor circuit as recited in claim 4 , wherein a distance between the gate electrodes of the first and second PMOS transistors as measured in a second direction is greater than a distance between the gate electrodes of the first and second NMOS transistors as measured in the second direction, the second direction perpendicular to the first direction.

6. A cross-coupled transistor circuit as recited in claim 4 , wherein a distance between the gate electrodes of the first and second NMOS transistors as measured in a second direction is greater than a distance between the gate electrodes of the first and second PMOS transistors as measured in the second direction, the second direction perpendicular to the first direction.

7. A cross-coupled transistor circuit as recited in claim 4 , wherein the first gate electrode is positioned a gate pitch distance away from the third gate electrode, the gate pitch distance measured in a second direction perpendicular to the first direction.

8. A cross-coupled transistor circuit as recited in claim 7 , wherein a distance between a centerline of the first gate electrode and a centerline of the second gate electrode as measured in the second direction is a multiple of the gate pitch distance.

9. A cross-coupled transistor circuit as recited in claim 8 , wherein the multiple of the gate pitch distance is an integer multiple.

10. A cross-coupled transistor circuit as recited in claim 4 , wherein the gate electrode of the first PMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second PMOS transistor.

11. A cross-coupled transistor circuit as recited in claim 4 , wherein the gate electrode of the first PMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second PMOS transistor, and wherein the gate electrode of the first PMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second PMOS transistor.

12. A cross-coupled transistor circuit as recited in claim 10 , wherein the gate electrode of the first NMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second NMOS transistor.

13. A cross-coupled transistor circuit as recited in claim 4 , wherein the gate electrode of the first NMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second NMOS transistor, and wherein the gate electrode of the first NMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second NMOS transistor.

14. A cross-coupled transistor circuit as recited in claim 4 , wherein the gate electrode of the first PMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second PMOS transistor, wherein the gate electrode of the first NMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second NMOS transistor.

15. A cross-coupled transistor circuit as recited in claim 4 , wherein the gate electrode of the first PMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second PMOS transistor, wherein the gate electrode of the first NMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second NMOS transistor, and wherein the gate electrode of the first NMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second NMOS transistor.

16. A cross-coupled transistor circuit as recited in claim 4 , wherein the gate electrode of the first PMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second PMOS transistor, and wherein the gate electrode of the first PMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second PMOS transistor, wherein the gate electrode of the first NMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second NMOS transistor.

17. A cross-coupled transistor circuit as recited in claim 4 , wherein the gate electrode of the first PMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second PMOS transistor, and wherein the gate electrode of the first PMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second PMOS transistor, wherein the gate electrode of the first NMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second NMOS transistor, and wherein the gate electrode of the first NMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second NMOS transistor.

18. A cross-coupled transistor circuit as recited in claim 1 , wherein the first and second PMOS transistors are collectively separated from the first and second NMOS transistors by an inner region, wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to each other through a first set of one or more conductive structures positioned within the inner region.

19. A cross-coupled transistor circuit as recited in claim 18 , wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to each other through a second set of one or more conductive structures positioned within the inner region, the second set of one or more conductive structures exclusive of the first set of one or more conductive structures.

20. A cross-coupled transistor circuit, comprising:
a first PMO

Assignees

• Becker Scott T
• Mali Jim
• Lambert Carole
• Tela Innovations Inc

Inventors

• Becker Scott T
• Mali Jim
• Lambert Carole

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L2924/00

  Electricity · mapped topic

• G06F17/5072

  Physics · mapped topic

• H01L23/528

  Electricity · mapped topic