RF amplifier with conductor-less region underlying filter circuit inductor, and methods of manufacture thereof

Patent metadata

Field	Value
Publication number	US-10637400-B2
Application number	US-201816121742-A
Country	US
Kind code	B2
Filing date	Sep 5, 2018
Priority date	Mar 24, 2015
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.

First claim

What is claimed is:

1. A semiconductor die comprising:
a semiconductor substrate having a top substrate surface and a bottom substrate surface;
a first conductive feature coupled to the bottom substrate surface, wherein the first conductive feature spans a first portion of the bottom substrate surface, and a first conductor-less region in which the conductive feature is not present spans a second portion of the bottom substrate surface;
a first transistor at the top substrate surface, wherein the first transistor is electrically connected to the first conductive feature, and the first transistor includes a first current conducting region within the semiconductor substrate, a second current conducting region within the semiconductor substrate, a first control terminal, a first current conducting terminal connected to the first current conducting region, and a second current conducting terminal connected to the second current conducting region; and
a first inductor electrically coupled to the second current conducting terminal, wherein the first inductor is coupled to the semiconductor substrate over a portion of the top substrate surface that is directly opposite the second portion of the bottom substrate surface that is spanned by the first conductor-less region.

2. The semiconductor die of claim 1 , wherein:
the first conductive feature forms a portion of a patterned conductive layer coupled to the bottom substrate surface.

3. The semiconductor die of claim 2 , wherein:
the patterned conductive layer has a thickness in a range of 10 microns to 50 microns.

4. The semiconductor die of claim 1 , wherein the first inductor is monolithic with the semiconductor die, and the first inductor is a spiral inductor comprising portions of one or more conductive layers formed over the top substrate surface.

5. The semiconductor die of claim 1 , wherein the first inductor forms a portion of a first filter circuit that is selected from a low pass filter circuit, a high pass filter circuit, and a band pass filter circuit.

6. The semiconductor die of claim 1 , further comprising:
a second conductive feature coupled to the bottom substrate surface and physically separated from the first conductive feature across the first conductor-less region, wherein the first current conducting terminal is electrically coupled to the first conductive feature, and the second current conducting terminal is electrically coupled to the second conductive feature.

7. The semiconductor die of claim 6 , wherein the second current conducting terminal is electrically coupled to the second conductive feature with at least one conductive structure selected from a through substrate via (TSV) and a wrap-around termination.

8. The semiconductor die of claim 6 , wherein:
the first and second conductive features form portions of a patterned conductive layer coupled to the bottom substrate surface.

9. The semiconductor die of claim 6 , wherein:
the first inductor has first and second inductor terminals,
the first inductor terminal is electrically coupled to the second current conducting terminal and to the second conductive feature,
the semiconductor die further includes a capacitor with first and second capacitor plates,
the first capacitor plate is electrically coupled to the second inductor terminal at a radio frequency (RF) cold point node, and
the second capacitor plate is electrically coupled to the first conductive feature.

10. The semiconductor die of claim 9 , further comprising:
a third conductive feature coupled to the bottom substrate surface and physically separated from the first and second conductive features across the bottom substrate surface, wherein the RF cold point node is electrically coupled to the third conductive feature.

11. The semiconductor die of claim 1 , further comprising:
a second conductor-less region in which the conductive feature is not present spanning a third portion of the bottom substrate surface; and
a second inductor electrically coupled to the first control terminal, wherein the second inductor is coupled to the semiconductor substrate over a portion of the top substrate surface that is directly opposite the third portion of the bottom substrate surface that is spanned by the second conductor-less region.

12. The semiconductor die of claim 11 , further comprising:
a second conductive feature coupled to the bottom substrate surface and physically separated from the first conductive feature across the first conductor-less region; and
a third conductive feature coupled to the bottom substrate surface and physically separated from the first conductive feature across the second conductor-less region, wherein the first current conducting terminal is electrically coupled to the first conductive feature, the second current conducting terminal is electrically coupled to the second conductive feature, and the first control terminal is electrically coupled to the third conductive feature.

13. The semiconductor die of claim 12 , further comprising:
a first conductive lead coupled to the second conductive feature; and
a second conductive lead coupled to the third conductive feature.

14. The semiconductor die of claim 1 , further comprising:
a second transistor at the top substrate surface, wherein the second transistor is electrically connected to the first conductive feature, and the second transistor includes a third current conducting region within the semiconductor substrate, a fourth current conducting region within the semiconductor substrate, a second control terminal, a third current conducting terminal connected to the third current conducting region, and a fourth current conducting terminal connected to the fourth current conducting region; and
a second inductor electrically coupled to the fourth current conducting terminal, wherein the second inductor is coupled to the semiconductor substrate over the portion of the top substrate surface that is directly opposite the second portion of the bottom substrate surface that is spanned by the first conductor-less region.

15. The semiconductor die of claim 1 , wherein the semiconductor substrate is a high resistivity substrate.

16. A method of forming a semiconductor die, the method comprising the steps of:
forming a transistor at a top substrate surface of a semiconductor substrate, wherein the transistor includes a control terminal, a first current conducting terminal, and a second current conducting terminal;
electrically coupling a first inductor to the second current conducting terminal, wherein the first inductor is positioned over a portion of the top substrate surface; and
coupling a first conductive feature to a bottom substrate surface of the semiconductor substrate, wherein the first conductive feature only partially covers the bottom substrate surface to define a first conductor-less region that spans a first portion of the bottom substrate surface that underlies the first inductor, and wherein the first conductive feature is electrically coupled to the transistor.

17. The method of claim 16 , wherein electrically coupling the first inductor comprises:
forming the first inductor over the portion of the top substrate surface as a spiral inductor comprising portions of one or more conductive layers coupled to the top substrate surface.

18. The method of claim 16 , further comprising:
coupling a second conductive feature to the bottom substrate surface, wherein the second conductive feature is electrically coupled to the first inductor and to the second current conducting termi

Assignees

• Nxp Usa Inc

Inventors

• Jones Jeffrey K
• Abdo David F
• Noori Basim H

Classifications

• H03F2200/222

  A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F2200/108

  A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F2203/21112

  A filter circuit being added at the input of a power amplifier stage · CPC title