Semiconductor device provided with direction sensor elements

Patent metadata

Field	Value
Publication number	US-9476949-B2
Application number	US-201414450896-A
Country	US
Kind code	B2
Filing date	Aug 4, 2014
Priority date	Aug 5, 2013
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A semiconductor device is provided with a substrate including a main surface and a back surface that face in opposite directions to each other in a thickness direction, and first, second and third direction sensor elements having different detection reference axes from each other. The substrate is formed with a recessed portion that is recessed from the main surface toward the back surface side. The first direction sensor element is disposed at least partially within the recessed portion. The second direction sensor element is disposed so as to overlap with the main surface as viewed in the thickness direction.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate including a main surface and a back surface that face in opposite directions to each other in a thickness direction; and
first, second and third direction sensor elements having different detection reference axes from each other;
wherein the substrate is formed with a recessed portion that is recessed from the main surface toward the back surface,
the first direction sensor element is disposed at least partially within the recessed portion, and the second direction sensor element is disposed so as to overlap with the main surface as viewed in the thickness direction.

2. The semiconductor device according to claim 1 , wherein the third direction sensor element is disposed so as to overlap with the main surface as viewed in the thickness direction.

3. The semiconductor device according to claim 2 , wherein the detection reference axis of the first direction sensor element extends in the thickness direction.

4. The semiconductor device according to claim 2 , wherein the detection reference axis of the second direction sensor element is parallel to the main surface.

5. The semiconductor device according to claim 2 , wherein the detection reference axis of the third direction sensor element is parallel to the main surface.

6. The semiconductor device according to claim 2 , wherein the detection reference axes of the first, second and third direction sensor elements are at right angles to each other.

7. The semiconductor device according to claim 2 , further comprising an integrated circuit element that is interposed between the main surface and the second direction sensor element.

8. The semiconductor device according to claim 7 , wherein part of the first direction sensor element projects from the main surface of the substrate in the thickness direction.

9. The semiconductor device according to claim 8 , wherein the recessed portion has a bottom surface that is located between the main surface and the back surface in the thickness direction, and the first direction sensor element is supported by the bottom surface.

10. The semiconductor device according to claim 9 , wherein the recessed portion includes an inner surface that is connected to the main surface.

11. The semiconductor device according to claim 10 , wherein the inner surface slopes in the thickness direction.

12. The semiconductor device according to claim 11 , wherein the recessed portion includes a curved surface connecting the bottom surface and the inner surface.

13. The semiconductor device according to claim 9 , wherein the substrate includes a base material that constitutes the main surface and the back surface, the base material being provided with a wiring pattern.

14. The semiconductor device according to claim 13 , wherein the wiring pattern includes an intermediate layer that is located between the main surface and the back surface in the thickness direction, and the intermediate layer includes a blocking portion that constitutes the bottom surface of the recessed portion.

15. The semiconductor device according to claim 14 , wherein the blocking portion is larger than the bottom surface as viewed in the thickness direction.

16. The semiconductor device according to claim 15 , wherein the base material includes a portion that is located between the intermediate layer and the back surface.

17. The semiconductor device according to claim 16 , wherein the wiring pattern includes a plurality of back surface electrodes that are exposed at the back surface.

18. The semiconductor device according to claim 17 , wherein at least one of the plurality of back surface electrodes overlaps with the blocking portion as viewed in the thickness direction.

19. The semiconductor device according to claim 17 , wherein the blocking portion and the plurality of back surface electrodes are insulated from each other.

20. The semiconductor device according to claim 1 , wherein the substrate includes one lateral surface having formed therein an opening that communicates with the recessed portion.

21. The semiconductor device according to claim 1 , wherein the substrate includes two lateral surfaces each having formed therein an opening that communicates with the recessed portion.

22. The semiconductor device according to claim 1 , wherein the recessed portion is separated from all lateral surfaces of the substrate.

23. The semiconductor device according to claim 13 , wherein the blocking portion is exposed at the back surface.

24. The semiconductor device according to claim 23 , wherein the first direction sensor element, the second direction sensor element, the third direction sensor element and the integrated circuit element each have a plurality of pads, and
the wiring pattern includes a plurality of pads that are exposed at the main surface.

25. The semiconductor device according to claim 24 , further comprising: a wire including a first bonding portion and a second bonding portion; and a bump;
wherein the first bonding portion is connected to one pad of the first direction sensor element, and the second bonding portion is connected to one pad of the integrated circuit element via the bump.

26. The semiconductor device according to claim 24 , further comprising a wire including a first bonding portion and a second bonding portion,
wherein the first bonding portion is connected to one pad of the first direction sensor element, and the second bonding portion is connected to one pad of the wiring pattern.

27. The semiconductor device according to claim 24 , further comprising: a wire including a first bonding portion and a second bonding portion; and a bump;
wherein the first bonding portion is connected to one pad of the integrated circuit element, and the second bonding portion is connected to one pad of one of the second direction sensor element and the third direction sensor element via the bump.

28. The semiconductor device according to claim 24 , further comprising a wire including a first bonding portion and a second bonding portion,
wherein the first bonding portion is connected to one pad of the integrated circuit element, and the second bonding portion is connected to one pad of the wiring pattern.

29. The semiconductor device according to claim 28 , further comprising: an additional wire including a first bonding portion and a second bonding portion; and a bump;
wherein the first bonding portion of the additional wire is connected to one pad of the wiring pattern, and the second bonding portion of the additional wire is connected to one pad of the integrated circuit element via the bump.

30. The semiconductor device according to claim 1 , further comprising a resin sealing portion that covers the first direction sensor element, the second direction sensor element and the third direction sensor element, wherein part of the resin sealing portion fills the recessed portion.

31. The semiconductor device according to claim 30 , wherein the substrate includes a lateral surface connecting the main surface and the back surface, and the resin sealing portion includes a lateral surface that is flush with the lateral surface of the substrate.

Assignees

• Rohm Co Ltd

Inventors

• Nishioka Taro
• Yamagami Mamoru

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/5434

  the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title