Stacked switch circuit having shoot through current protection

Patent metadata

Field	Value
Publication number	US-10637236-B2
Application number	US-201816195616-A
Country	US
Kind code	B2
Filing date	Nov 19, 2018
Priority date	Jun 27, 2016
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

An apparatus is described. The apparatus includes a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage.

First claim

The invention claimed is:

1. An apparatus, comprising:
a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage, the stacked switch circuit comprising an isolated internal node residing on a current path that connects respective channel ends of first and second transistors, the current path not including a branch for current through a component of the stacked switch circuit other than the first and second transistors, the terminals of the switch respectively coupled to other channel ends of the first and second transistors.

2. The apparatus of claim 1 wherein the protection circuitry keeps at least one of the first and second transistors off during the switch.

3. The apparatus of claim 2 wherein when the stacked switch circuit is in the off state the protection circuitry keeps off a one of the first and second transistors that was off in a first steady state when the one terminal of the switch had the higher voltage until the other of the first and second transistors that will be off in a second steady state when the other terminal of the switch has the higher voltage is off.

4. The apparatus of claim 1 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply a higher of the respective voltages at the terminals of the switch to a gate of one of the first and second transistors that is closer to the terminal of the switch that receives the higher of the respective voltages.

5. The apparatus of claim 4 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply the higher of the respective voltages less a second voltage to a gate of the other of the first and second transistors that receives a lesser of the respective voltages at the terminals of the switch.

6. The apparatus of claim 5 wherein application of the higher of the respective voltages less the second voltage to the gate of the other of the first and second transistors prevents the other transistor from exceeding a maximum rating.

7. An apparatus, comprising:
a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage, wherein, the stacked switch circuit has first and second halves that mirror each other and the protection circuitry couples the first and second halves, and wherein, the stacked switch circuit comprises an isolated internal node residing on a current path that connects respective channel ends of first and second transistors, the current path not including a branch for current through a component of the stacked switch circuit other than the first and second transistors, the terminals of the switch respectively coupled to other channel ends of the first and second transistors.

8. The apparatus of claim 7 wherein the protection circuitry keeps at least one of the first and second transistors off during the switch.

9. The apparatus of claim 8 wherein when the stacked switch circuit is in the off state the protection circuitry keeps off one of the first and second transistors that was off in a first steady state when the one terminal of the switch had the higher voltage until the other of the first and second transistors that will be off in a second steady state when the other terminal of the switch has the higher voltage is off.

10. The apparatus of claim 7 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply a higher of the respective voltages at the terminals of the switch to a gate of one of the first and second transistors that is closer to the terminal of the switch that receives the higher of the respective voltages.

11. The apparatus of claim 10 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply the higher of the respective voltages less a second voltage to a gate of the other of the first and second transistors that receives a lesser of the respective voltages at the terminals of the switch.

12. The apparatus of claim 11 wherein application of the higher of the respective voltages less the second voltage to the gate of the other of the first and second transistor prevents the other transistor from exceeding a maximum rating.

13. A computing system, comprising:
one or more processing cores;
a system memory;
a memory controller coupled to the system memory;
power supply circuitry, the power supply circuitry comprising a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage, the stacked switch circuit comprising an isolated internal node residing on a current path that connects respective channel ends of first and second transistors, the current path not including a branch for current through a component of the stacked switch circuit other than the first and second transistors, the terminals of the switch respectively coupled to other channel ends of the first and second transistors.

14. The apparatus of claim 13 wherein the protection circuitry keeps at least one of the first and second transistors off during the switch.

15. The apparatus of claim 14 wherein when the stacked switch circuit is in the off state the protection circuitry keeps off one of the first and second transistors that was off in a first steady state when the one terminal of the switch had the higher voltage until the other of the first and second transistors that will be off in a second steady state when the other terminal of the switch has the higher voltage is off.

16. The apparatus of claim 13 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply a higher of the respective voltages at the terminals of the switch to a gate of one of the first and second transistors that is closer to the terminal of the switch that receives the higher of the respective voltages.

17. The apparatus of claim 16 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply the higher of the respective voltages less a second voltage to a gate of the other of the first and second transistors that receives a lesser of the respective voltages at the terminals of the switch.

18. The apparatus of claim 17 wherein application of the higher of the respective voltages less the second voltage to the gate of the other of the first and second transistor prevents the other transistor from exceeding a maximum rating.

Assignees

• Intel Ip Corp

Inventors

• Hulub Marian
• Daniel Marcin

Classifications

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• H03K19/00361 Primary

  in field effect transistor circuits · CPC title

• H02H11/007 Primary

  involving automatic switching for adapting the protected apparatus to the supply voltage · CPC title

• H01L29/00

  Electricity · mapped topic

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title