Thermal sensor including pulse-width modulation output

Patent metadata

Field	Value
Publication number	US-9816871-B2
Application number	US-201514865490-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Some embodiments include apparatuses and methods having a node to receive ground potential, a first diode including an anode coupled to the node, a second diode including an anode coupled to the node, a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition, and a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode. At least one of such the embodiments includes a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.

First claim

The invention claimed is:

1. An apparatus comprising:
a node to receive ground potential;
a first diode including an anode coupled to the node;
a second diode including an anode coupled to the node;
a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition, the first circuit including a capacitor coupled to the cathode of the first diode; and
a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode.

2. The apparatus of claim 1 , further comprising a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.

3. The apparatus of claim 1 , wherein the first and second diodes are arranged to be biased with different current densities.

4. The apparatus of claim 1 , wherein the first circuit is arranged to cause the first and second diodes to be in the forward-bias condition at different times.

5. An apparatus comprising:
a node to receive ground potential;
a first diode including an anode coupled to the node;
a second diode including an anode coupled to the node:
a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition; and
a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode, wherein the first circuit includes a capacitor and the circuit is arranged to:
charge a first plate of the capacitor when a second plate of the capacitor is coupled to the node; and
decouple the second plate from the node and couple the first plate to the node to generate the voltage applied to the cathode of one of the first and second diodes.

6. The apparatus of claim 5 , wherein the capacitor is charged for an amount of time until the first plate reaches a reference voltage, and the duty cycle of the signal is based on the amount of time.

7. An apparatus comprising:
a node to receive ground potential;
a first diode including an anode coupled to the node;
a second diode including an anode coupled to the node;
a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition; and
a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode, wherein the first circuit includes:
a first capacitor coupled to the first diode;
a second capacitor coupled to the second diode;
a first p-channel transistor coupled between the first capacitor and the node; and
a second p-channel transistor coupled between the second capacitor and the node.

8. The apparatus of claim 7 , wherein a gate of the first p-channel transistor is coupled to the cathode of the second diode, and a gate of the second p-channel transistor is coupled to the cathode of the first diode.

9. The apparatus of claim 8 , wherein the first circuit includes a first additional capacitor coupled to the gate of the first p-channel transistor, and a second additional capacitor coupled to the gate of the second p-channel transistor.

10. An apparatus comprising:
a first material;
a first diode and a second diode, each of the first and second diodes including a p-n junction formed from a portion of the first material and a portion of a second material;
a first circuit to generate a negative voltage and apply the negative voltage to the first and second diodes to alternately cause the first and second diodes to be in a forward-bias condition, the first circuit including a capacitor coupled to a cathode of the first diode; and
a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode.

11. The apparatus of claim 10 , wherein the first material is included in a substrate, and the second material is part of an n-well formed in the substrate.

12. The apparatus of claim 10 , wherein the first and second diodes have a size ratio different from one.

13. The apparatus of claim 10 , wherein the first circuit includes a charge pump to generate the negative voltage.

14. The apparatus of claim 10 , further comprising a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.

15. An apparatus comprising:
a first material;
a first diode and a second diode, each of the first and second diodes including a junction formed from a portion of the first material and a portion of a second material;
a first circuit to generate a negative voltage and apply the negative voltage to the first and second diodes to alternately cause the first and second diodes to be in a forward-bias condition; and
a second circuit to generate a sinal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode, wherein the first circuit includes a first capacitor coupled to the first diode and a second capacitor coupled to the second diode, and the first circuit is arranged to:
alternately charge a first plate of the first capacitor and a first plate of the second capacitor; and
alternately couple the first plate of the first capacitor and the first plate of the second capacitor to ground to alternately generate the negative voltage at a second plate of the first capacitor and a second plate of the second capacitor.

16. The apparatus of claim 15 , wherein the second circuit includes a comparator to compare a reference voltage with a voltage from the first plate of each of the first and second capacitors to generate pulses, such that the duty cycle of the signal is based on timing between the pulses.

17. The apparatus of claim 15 , further comprising a current source to provide a current to charge the first plate of each of the first and second capacitors.

18. An apparatus comprising:
a substrate including a p-type material;
a multi-gate transistor structure formed over the substrate;
a first diode and a second diode, each of the first and second diodes including a p-n junction formed a portion of the substrate and a portion of an n-type material formed over the substrate;
a first circuit to apply a negative voltage to the first and second diodes to alternately cause the first and second diodes to be in a forward-bias condition, the first circuit including a capacitor coupled to a cathode of the first diode; and
a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode.

19. The apparatus of claim 18 , wherein the multi-gate transistor structure includes tri-gate transistors.

20. The apparatus of claim 18 , wherein the multi-gate transistor structure includes finFET transistors.

21. The apparatus of claim 18 , further comprising a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.

Assignees

• Intel Corp
• Intel Ip Corp

Inventors

• Eberlein Matthias

Classifications

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• G01K7/01 Primary

  using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) · CPC title

• G01K7/42

  Circuits effecting compensation of thermal inertia; Circuits for predicting the stationary value of a temperature · CPC title

• H01L29/861

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic