Vertical memory device having an epitaxial layer in contact with a channel layer

Patent metadata

Field	Value
Publication number	US-10636808-B2
Application number	US-201815941978-A
Country	US
Kind code	B2
Filing date	Mar 30, 2018
Priority date	Jul 13, 2017
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.

First claim

What is claimed is:

1. A vertical memory device comprising:
a substrate;
a plurality of gate electrode layers stacked on the substrate;
a channel layer having a vertical portion and a connection portion extended from a lower end portion of the vertical portion, the vertical portion penetrating through the plurality of gate electrode layers;
a first epitaxial layer between the connection portion and the substrate;
a second epitaxial layer between the connection portion and the substrate; and
a gate dielectric layer including a first portion and a second portion extended from an lower end of the first portion,
wherein the first epitaxial layer is disposed between the second epitaxial layer and the connection portion of the channel layer,
wherein a width of the second epitaxial layer is greater than a width of the first epitaxial layer,
wherein the channel layer is a single layer,
wherein the connection portion of the channel layer covers an entire upper surface of the first epitaxial layer,
wherein the second epitaxial layer includes a sidewall and an upper surface,
wherein the sidewall of the second epitaxial layer and the upper surface of the second epitaxial layer are connected at obtuse angle,
wherein the first portion of the gate dielectric layer is disposed between the plurality of gate electrode layers and the vertical portion,
wherein the second portion of the gate dielectric layer is disposed between the connection portion and the second epitaxial layer, and
wherein a width of the connection portion is greater than the width of the first epitaxial layer.

2. The vertical memory device of claim 1 , wherein the first epitaxial layer penetrates through at least a portion of the gate dielectric layer and has an upper surface protruding beyond the gate dielectric layer.

3. The vertical memory device of claim 1 , wherein an upper surface of the first epitaxial layer has an upwardly convex curved surface.

4. The vertical memory device of claim 1 , wherein an upper surface of the first epitaxial layer has inclined surfaces.

5. The vertical memory device of claim 1 , wherein a lower surface of the first epitaxial layer has a downwardly convex curved surface.

6. The vertical memory device of claim 1 , wherein a lower surface of the first epitaxial layer has inclined surfaces.

7. The vertical memory device of claim 2 , wherein the first epitaxial layer comprises a first region penetrating entirely through the gate dielectric layer and having a first diameter, and a second region disposed on the first region and having a second diameter greater than the first diameter of the first region.

8. The vertical memory device of claim 1 , wherein a first upper surface of the first epitaxial layer is disposed to be higher than a second upper surface of a lowermost gate electrode layer, among the plurality of gate electrode layers.

9. The vertical memory device of claim 1 , wherein the single layer is in a singular in contact with the gate dielectric layer and the first epitaxial layer.

10. A vertical memory device comprising:
a substrate;
a plurality of gate electrode layers stacked on the substrate;
a channel hole penetrating through the plurality of gate electrode layers;
a channel layer extended in the channel hole in a vertical direction and having a vertical portion and a connection portion extended from an lower end portion of the vertical portion, the vertical portion penetrating through the plurality of gate electrode layers;
a gate dielectric layer including a sidewall portion and a lower surface portion, the sidewall portion being disposed between the channel layer and the plurality of gate electrode layers, and the lower surface portion being bent in a lower portion of the channel hole to be disposed between the channel layer and the substrate; and
a first epitaxial layer in contact with the channel layer and penetrating through the lower surface portion of the gate dielectric layer,
wherein the channel layer covers an entire upper surface of the first epitaxial layer and the first epitaxial layer has a diameter smaller than an external diameter of the channel layer,
wherein the first epitaxial layer includes a first portion protruding to be lower than the gate dielectric layer, a second portion disposed on the first portion and penetrating through the gate dielectric layer, and a third portion disposed on the second portion and between the second portion and the channel layer,
wherein a width of the third portion is greater than a width of the second portion.

11. The vertical memory device of claim 10 , wherein an upper surface of the first epitaxial layer and a lower surface of the first epitaxial layer have different forms.

12. The vertical memory device of claim 10 , wherein the channel layer is a single layer, and
wherein the single layer is in a singular in contact with the gate dielectric layer and the first epitaxial layer.

13. The vertical memory device of claim 10 , wherein a width of the connection portion of the channel layer is equal to the width of the third portion of the first epitaxial layer.

14. A vertical memory device comprising:
a substrate;
a plurality of gate electrode layers stacked on the substrate;
a channel hole penetrating through the plurality of gate electrode layers;
a gate dielectric layer covering an internal sidewall of the channel hole and bent in a lower portion of the channel hole;
a channel layer disposed on the gate dielectric layer extended in the channel hole in a vertical direction;
a through hole penetrating through the gate dielectric layer in the lower portion of the channel hole;
a first semiconductor layer filling at least a portion of the through hole and in contact with the channel layer; and
a second semiconductor layer disposed between the first semiconductor layer and the substrate,
wherein the channel layer covers an entire upper surface of the first semiconductor layer,
wherein the first semiconductor layer has a diameter smaller than an external diameter of the channel layer,
wherein the first semiconductor layer includes a first portion protruding to be lower than the gate dielectric layer, a second portion disposed on the first portion and penetrating through the gate dielectric layer, and a third portion disposed on the second portion and between the second portion and the channel layer,
wherein a width of the first portion is greater than a width of the second portion.

15. The vertical memory device of claim 14 , wherein the first semiconductor layer entirely fills the through hole, and an upper surface of the first semiconductor layer has an upwardly convex curved surface.

16. The vertical memory device of claim 14 , wherein the first semiconductor layer entirely fills the through hole, and an upper surface of the first semiconductor layer has inclined surfaces.

17. The vertical memory device of claim 14 , wherein
the single layer is in a singular in contact with the gate dielectric layer and the first semiconductor layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kyung Hwan
• Kim Yong Seok
• Kim Tae Hun
• Kim Byoung Taek
• Lim Jun Hee

Classifications

• H01L29/792

  Electricity · mapped topic

• H01L29/511

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L29/42348

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic