Metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure

Patent metadata

Field	Value
Publication number	US-9524977-B2
Application number	US-201514687403-A
Country	US
Kind code	B2
Filing date	Apr 15, 2015
Priority date	Apr 15, 2015
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Resistance of a semiconductor channel in three-dimensional memory stack structures can be reduced by forming a metal-semiconductor alloy region between a vertical semiconductor channel and a horizontal semiconductor channel located within a substrate. The metal-semiconductor alloy region can be formed by recessing a portion of the semiconductor material layer in the semiconductor substrate underneath a memory opening after formation of a memory film, selectively depositing a metallic material in the recess region, depositing a vertical semiconductor channel, and reacting the deposited metallic material with an adjacent portion of the semiconductor material layer and the vertical semiconductor channel. A sacrificial dielectric material layer can be formed on the memory film prior to the selective deposition of the metallic material. The vertical semiconductor channel can be formed in a single deposition process, thereby eliminating any interface therein and minimizing the resistance of the vertical semiconductor channel.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device, comprising:
a substrate including a semiconductor material;
a stack of alternating layers comprising insulator layers and electrically conductive layers located over the semiconductor material of the substrate;
a memory opening extending through the stack;
a semiconductor channel located within the memory opening;
a memory film located within the memory opening; and
a metal-semiconductor alloy region which is located between and contacts the semiconductor material of the substrate and the semiconductor channel,
wherein:
the metal-semiconductor alloy region comprises an alloy of the semiconductor material and at least one metal element;
the at least one metal element comprises a plurality of metal elements;
the metal-semiconductor alloy region comprises a variable composition of a first metal element and a second metal element that are among the plurality of metal elements;
a concentration of the first metal element decreases with a distance from an interface between the semiconductor material of the substrate and the metal-semiconductor alloy region; and
a concentration of the second metal element increases with the distance from the interface between the semiconductor material of the substrate and the metal-semiconductor alloy region.

2. The monolithic three-dimensional memory device of claim 1 , wherein:
the semiconductor channel comprises a vertically extending tubular portion located within the memory film, and a horizontal portion having a horizontal thickness and contacting a top surface of the metal-semiconductor alloy region; and
the semiconductor material of the substrate comprises at least one of:
an upper portion of a semiconductor wafer;
a semiconductor material layer located over an upper portion of the semiconductor wafer or over an upper portion of a non-semiconductor substrate;
a doped semiconductor well in the semiconductor wafer or in the semiconductor material layer; or
a doped semiconductor source line located in the semiconductor wafer or in the semiconductor material layer.

3. The monolithic three-dimensional memory device of claim 1 , wherein:
a vertical interface between the semiconductor material of the substrate and the metal-semiconductor alloy region is laterally offset from a sidewall of an opening through a horizontal portion of the memory film; and
the metal-semiconductor alloy region is at least partially embedded within semiconductor material of the substrate.

4. The monolithic three-dimensional memory device of claim 1 , wherein the at least one metal element is selected from cobalt, ruthenium, and tungsten, the semiconductor material comprises silicon, and the metal-semiconductor alloy region comprises a metal silicide of the at least one metal element.

5. The monolithic three-dimensional memory device of claim 1 , wherein at least a portion of an interface between the metal-semiconductor alloy region and the semiconductor channel is located above a bottom surface of the memory film.

6. The monolithic three-dimensional memory device of claim 5 , wherein:
a first portion of the metal-semiconductor alloy region extending through an opening in a horizontal portion of the memory film has a first width;
a second portion of the metal-semiconductor alloy region located below the bottom surface of the memory film has a second width; and
the second width is greater than the first width.

7. The monolithic three-dimensional memory device of claim 6 , wherein a periphery of the interface between the metal-semiconductor alloy region and the semiconductor channel either contacts a sidewall of the opening in the horizontal portion of the memory film or is located above the horizontal portion of the memory film.

8. The monolithic three-dimensional memory device of claim 1 , wherein:
the monolithic three-dimensional memory device is a vertical NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND memory device;
the substrate comprises a silicon substrate;
the vertical NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the three-dimensional array of NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels includes a semiconductor channel that extends substantially perpendicular to a top surface of the substrate; and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

9. A method of manufacturing a three-dimensional memory device, comprising:
forming a stack of alternating layers comprising first material layers and second material layers over a substrate that includes a semiconductor material;
forming a memory opening extending through the stack;
forming a memory film in the memory opening;
forming at least one metallic material on the semiconductor material of the substrate;
forming a semiconductor channel in the memory opening; and
forming a metal-semiconductor alloy region by reacting the at least one metallic material with a portion of the semiconductor material of the substrate,
wherein:
the metal-semiconductor alloy region is formed between, and contacts, the semiconductor material of the substrate and the semiconductor channel;
the first material layers comprise insulating layers;
the second material layers are replaced with electrically conductive layers to form a stack of alternating layers comprising the insulating layers and the electrically conductive layers;
the metal-semiconductor alloy region comprises an alloy of the semiconductor material and at least one metal element;
the at least one metal element comprises a plurality of metal elements;
the metal-semiconductor alloy region comprises a variable composition of a first metal element and a second metal element that are among the plurality of metal elements;
a concentration of the first metal element decreases with a distance from an interface between the semiconductor material of the substrate and the metal-semiconductor alloy region; and
a concentration of the second metal element increases with the distance from the interface between the semiconductor material of the substrate and the metal-semiconductor alloy region.

10. The method of claim 9 , further comprising recessing a portion of the semiconductor material of the substrate underneath the memory opening to form a recess region after forming the memory film.

11. The method of claim 10 , wherein:
forming the at least one metallic material comprises selectively depositing at least one metallic material on the semiconductor material of the substrate in the recess region while preventing depositing the at least one metallic material over the stack; and
forming the semiconductor channel comprises a single semiconductor material deposition process that is performed after forming the recess region and before forming the metal-semiconductor alloy region.

12. The method of claim 11 , wherein:
the single semiconductor material deposition process comprises an amorphous silicon layer deposition process; and
forming the metal-semiconductor alloy regi

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Sharangpani Rahul
• Makala Raghuveer S
• Koka Sateesh
• Kubo Tomohiro
• Ariyoshi Junichi
• Matamis George

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title